On May 5, 10:41*am, Topi <(E-Mail Removed)> wrote:

> Hi,

>

> I am a little surprised that the following code refuses to synthesize

> (at least with Quartus and Synopsys (Lattice's)):

>

> **********************

>

> library ieee;

> use ieee.std_logic_1164.all;

> use ieee.numeric_std.all;

>

> entity real_synth is

> * * * * port(

> * * * * * * * * a_in: in unsigned(15 downto 0);

> * * * * * * * * b_out: out unsigned(15 downto 0)

> * * * * );

> end;

>

> architecture synth of real_synth is

> begin

> * * * * process(a_in)

> * * * * * * * * variable r: real;

> * * * * begin

> * * * * * * * * r := real(to_integer(a_in));

> * * * * * * * * r := r*1.2;

> * * * * * * * * if r<0.0 then

> * * * * * * * * * * * * r := 0.0;

> * * * * * * * * elsif r>65535.0 then

> * * * * * * * * * * * * r := 65535.0;

> * * * * * * * * end if;

> * * * * * * * * b_out <= to_unsigned(integer(r),16);

> * * * * end process;

> end;

>

> ****************************

>

> Ok, I do understand that real values are a problem when they need to

> be stored, or transported (with signals/ports).

>

> But in this case the mapping of a_in => b_out can be evaluated by

> brute force (by going through all input states, and running the code

> inside the process for every possible input combination and noting the

> output values).

>

> Upto today I had thought that all synthesizers would fallback to the

> brute force method if intelligent algorithm generator fails. It seems

> that I had mistrusted them, though.

>

> Any ideas why the synthesizers DO NOT have this brute-force fallback

> method?

>

> - Topi
Real types are not appropriate for synthesis in any shape or form.

There is no definition of how they exist in binary (because it is not

an array type) and so cannot be synthesised into gates and register.

You will have to convert your real values to fixed point. Try looking

at the new IEEE fixed packages. 93 compatible versions of the library

can be found here:

http://www.vhdl.org/fphdl/