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Proper index type to access an std_logic array

 
 
sylwa sylwa is offline
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Join Date: Apr 2011
Posts: 2
 
      04-18-2011
Hi !

I get the error "Line 65. Wrong index type for pipeline." when I try to synthesize.
Concerned line is : "pipeline(index) <= input;"

Here is my snippet :

Quote:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package pck_justToDeclareANewType is
type arrayOfLogicVector is array (natural range <>, natural range <>) of STD_LOGIC;
--type arrayOfLogicVector is array (natural range <>) of STD_LOGIC_vector(0 to 3);
end pck_justToDeclareANewType;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.pck_justToDeclareANewType.all;

entity genericDelay is
generic ( busWidth : positive range 1 to 32 := 1;
delay_in_clocks : natural range 0 to 1024 := 0 );
Port ( inClock : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-- o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-
output : out STD_LOGIC_VECTOR (busWidth-1 downto 0) );
end genericDelay;

architecture Behavioral of genericDelay is

signal pipeline : arrayOfLogicVector (delay_in_clocks downto 0, busWidth-1 downto 0);
begin

-- main synchrone process
delayer : process (inClock )
begin
if rising_edge( inClock ) then
L1 : for index in 0 to delay_in_clocks loop
pipeline(index) <= input;
end loop L1;
end if;
end process;

end Behavioral;
May I ask you some help please ?

Regards

Sylvain
 
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eliascm eliascm is offline
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Join Date: Jan 2009
Posts: 42
 
      04-19-2011
You have 2 indices on your array, but you are trying to access it with a single index.
 
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sylwa sylwa is offline
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Join Date: Apr 2011
Posts: 2
 
      04-21-2011
Many thanks eliascm !
I thought that if I used only the first index, I could access to a full vector of bits.

I went wrong with such following type :
type arrayOfLogicVector is array (natural range <> ) of STD_LOGIC_vector( busWidth - 1 downto 0) ;

where only one index is enough to access to a full vector of bits.

Cheers !

Sylvain
 
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