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Synthesis of Logic on Non-boolean Constants

 
 
rickman
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      03-29-2011
I was using some logic to shorten typing of some operations where I
was trying to create tristate drivers. To be sure of the result I
looked up the logic tables and found that, for example the OR function
on a constant 'z' and a signal produces a '1' when the signal is a
'1', but when the signal is a zero results in an 'x'. This is not the
same as a 'z' obviously, which is what I wanted. Clearly this is not
a good idea even if it is shorter to type.

But I realized, how do I know what will be synthesized by this
expression? Then I came to my senses and realized I just needed to
use the IF statement and not worry about brevity.

Reading the sysnthesis standard 1076.6 it says,

'Three-state logic shall be modeled when an object, or an element of
the object, is explicitly assigned the IEEE Std 1164-1993 value Z.
The assignment to Z shall be a conditional assignment; that is,
assignment occurs under the control of a condition.'

So trying to get a logic function to do the job of a conditional
assignment just won't work, eh?

Rick
 
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Andy
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      03-29-2011
Using an existing operator may not work, but you could write a
function that encapsulates the conditional assignment.

For example:
ts_out <= bufz(input, enable);

You could also overload bufz() for SL and SLV inputs & return values
(and SL and SLV [bitwise] enables).

Andy
 
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rickman
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      03-30-2011
On Mar 29, 5:00*pm, Andy <(E-Mail Removed)> wrote:
> Using an existing operator may not work, but you could write a
> function that encapsulates the conditional assignment.
>
> For example:
> ts_out <= bufz(input, enable);
>
> You could also overload bufz() for SL and SLV inputs & return values
> (and SL and SLV [bitwise] enables).
>
> Andy


I found something that seems odd to me. I often forget details of a
language when it is something that I don't use very often. I thought
that VHDL did not care about case in all situations. But in the case
of std_logic it would seem to care if the values assigned are 'x' or
'X' and 'z' or 'Z'! I was getting errors on assignments and
comparisons along with a seemingly unrelated error in a separate file
having to do with some intermediate conversion step that didn't
involve the source code. When I changed the case to upper for the
literals, it all worked again.

I guess all these years I haven't made the mistake of using lower case
for these values or possibly the other tools I've used don't care
about the difference.

Rick
 
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Jonathan Bromley
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      03-30-2011
On Mar 30, 4:55*am, rickman <(E-Mail Removed)> wrote:

> I found something that seems odd to me. *I often forget details of a
> language when it is something that I don't use very often. *I thought
> that VHDL did not care about case in all situations. *But in the case
> of std_logic it would seem to care if the values assigned are 'x' or
> 'X' and 'z' or 'Z'! *I was getting errors on assignments and
> comparisons along with a seemingly unrelated error in a separate file
> having to do with some intermediate conversion step that didn't
> involve the source code. *When I changed the case to upper for the
> literals, it all worked again.
>
> I guess all these years I haven't made the mistake of using lower case
> for these values or possibly the other tools I've used don't care
> about the difference.


heh! VHDL is completely case-insensitive
BUT the values 'X', '0' etc for std_logic
are in fact CHARACTER LITERALS and therefore
they ARE case-sensitive. 'z' is not one of
the literals in the std_(u)logic set of 9
values. By contrast, if you have an
enumeration type (like for a state machine)
then the values of that type are ordinary
VHDL identifiers like IDLE_STATE and they
are NOT case-sensitive. You can use character
literals as the enumeration values in your
own enum types if you wish...
type foo is ('a', 'b', 'c');
but almost no-one ever does that.

And the really funny thing is... Verilog is a
case-sensitive language in every respect,
EXCEPT that its numeric bit values X and Z
(and its radix specifiers 'b, 'h etc) are
NOT case sensitive. Exactly the opposite
way round from VHDL.

Any tool that gets this wrong is non-compliant;
it must simply be that you've not made that mistake
before. I blame your exposure to Verilog
--
Jonathan Bromley
 
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Thomas Stanka
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      03-30-2011
On 29 Mrz., 18:13, rickman <(E-Mail Removed)> wrote:
> I was using some logic to shorten typing of some operations where I
> was trying to create tristate drivers. *To be sure of the result I
> looked up the logic tables and found that, for example the OR function
> on a constant 'z' and a signal produces a '1' when the signal is a
> '1', but when the signal is a zero results in an 'x'. *This is not the
> same as a 'z' obviously, which is what I wanted. *Clearly this is not
> a good idea even if it is shorter to type.


So want the technology to contain a buffer that has an high impedance
output in case of one input is high impedance?
But else the output needs to be low impedance either driving '0' or
'1'. Seems quite unusual to be found in any tech library.

Your problems seems to me not vhdl related, instead you need to think
in dedicated hardware functionality.
It is quite easy to construct a logic function in vhdl that helps your
need for simulation purpose, but quite a hard job, to build the needed
transistor structure to implement the vhdl in real silicon.

best regards Thomas


 
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rickman
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      03-30-2011
On Mar 30, 8:43*am, Jonathan Bromley <(E-Mail Removed)>
wrote:
> On Mar 30, 4:55*am, rickman <(E-Mail Removed)> wrote:
>
> > I found something that seems odd to me. *I often forget details of a
> > language when it is something that I don't use very often. *I thought
> > that VHDL did not care about case in all situations. *But in the case
> > of std_logic it would seem to care if the values assigned are 'x' or
> > 'X' and 'z' or 'Z'! *I was getting errors on assignments and
> > comparisons along with a seemingly unrelated error in a separate file
> > having to do with some intermediate conversion step that didn't
> > involve the source code. *When I changed the case to upper for the
> > literals, it all worked again.

>
> > I guess all these years I haven't made the mistake of using lower case
> > for these values or possibly the other tools I've used don't care
> > about the difference.

>
> heh! *VHDL is completely case-insensitive
> BUT the values 'X', '0' etc for std_logic
> are in fact CHARACTER LITERALS and therefore
> they ARE case-sensitive. *'z' is not one of
> the literals in the std_(u)logic set of 9
> values. *By contrast, if you have an
> enumeration type (like for a state machine)
> then the values of that type are ordinary
> VHDL identifiers like IDLE_STATE and they
> are NOT case-sensitive. *You can use character
> literals as the enumeration values in your
> own enum types if you wish...
> * *type foo is ('a', 'b', 'c');
> but almost no-one ever does that.
>
> And the really funny thing is... Verilog is a
> case-sensitive language in every respect,
> EXCEPT that its numeric bit values X and Z
> (and its radix specifiers 'b, 'h etc) are
> NOT case sensitive. *Exactly the opposite
> way round from VHDL.
>
> Any tool that gets this wrong is non-compliant;
> it must simply be that you've not made that mistake
> before. *I blame your exposure to Verilog
> --
> Jonathan Bromley


Nice try, but my exposure to Verilog is pretty minimal in this
context. :^p

Actually, if this test bench and test fixture hadn't already been
coded in VHDL, I would have likely done it in Verilog as a further
part of my exploration into Verilog. I did a small project a month or
two ago and was pretty happy with Verilog. Test benches are an area
in Verilog I want to explore further. The test bench I did for the
project was pretty limited, reading some hex values from a file to
drive an SPI port. This test bench is a lot more complicated having
to read commands as well as numerical data from a file. It also has a
lot more going on requiring synchronization between all the parts.

I have a CPU design that I may be returning to later this year. I'm
thinking of recoding it to improve efficiency and may swing a Verilog
bat at that pitch. Who knows, I may hit a home run!

I also want to explore the Silicon Blue devices a bit more and will
likely try their parts to test the implementation. I don't recall
much about their eval board, but I think they are a bit pricey. I may
use one of those super low cost PCB services like DorkbotPDX to create
my own board. There is another part from Green Arrays that I might
want to explore as well.

Rick
 
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rickman
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      03-30-2011
On Mar 30, 8:49*am, Thomas Stanka <(E-Mail Removed)>
wrote:
> On 29 Mrz., 18:13, rickman <(E-Mail Removed)> wrote:
>
> > I was using some logic to shorten typing of some operations where I
> > was trying to create tristate drivers. *To be sure of the result I
> > looked up the logic tables and found that, for example the OR function
> > on a constant 'z' and a signal produces a '1' when the signal is a
> > '1', but when the signal is a zero results in an 'x'. *This is not the
> > same as a 'z' obviously, which is what I wanted. *Clearly this is not
> > a good idea even if it is shorter to type.

>
> So want the technology to contain a buffer that has an high impedance
> output in case of one input is high impedance?
> But else the output needs to be low impedance either driving '0' or
> '1'. Seems quite unusual to be found in any tech library.
>
> Your problems seems to me not vhdl related, instead you need to think
> in dedicated hardware functionality.
> It is quite easy to construct a logic function in vhdl that helps your
> need for simulation purpose, but quite a hard job, to build the needed
> transistor structure to implement the vhdl in real silicon.
>
> best regards Thomas


That's funny, I have some parts on a current board design that do
pretty much this. They are called switches. One of the inputs will
cause a 'Z' on the output when the input is a 'Z'. A little logic
added to the control input and it would do exactly what I was coding.

Rick
 
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Thomas Stanka
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Posts: n/a
 
      03-31-2011
On 30 Mrz., 17:04, rickman <(E-Mail Removed)> wrote:
> On Mar 30, 8:49*am, Thomas Stanka <(E-Mail Removed)>
> wrote:
>
>
>
> > On 29 Mrz., 18:13, rickman <(E-Mail Removed)> wrote:

>
> > > I was using some logic to shorten typing of some operations where I
> > > was trying to create tristate drivers. *To be sure of the result I
> > > looked up the logic tables and found that, for example the OR function
> > > on a constant 'z' and a signal produces a '1' when the signal is a
> > > '1', but when the signal is a zero results in an 'x'. *This is not the
> > > same as a 'z' obviously, which is what I wanted. *Clearly this is not
> > > a good idea even if it is shorter to type.

>
> > So want the technology to contain a buffer that has an high impedance
> > output in case of one input is high impedance?
> > But else the output needs to be low impedance either driving '0' or
> > '1'. Seems quite unusual to be found in any tech library.

>
> > Your problems seems to me not vhdl related, instead you need to think
> > in dedicated hardware functionality.
> > It is quite easy to construct a logic function in vhdl that helps your
> > need for simulation purpose, but quite a hard job, to build the needed
> > transistor structure to implement the vhdl in real silicon.

>
> > best regards Thomas

>
> That's funny, I have some parts on a current board design that do
> pretty much this. *They are called switches. *One of the inputs will
> cause a 'Z' on the output when the input is a 'Z'. *A little logic
> added to the control input and it would do exactly what I was coding.


Actually there is a difference between whats possible on a PCB, whats
possible with dedicated structures in a device and whats possible
using a given cell library.

Your synthesis tool is only able to map a logic to the defined logic
elements. And in fact the tool tends to be quite stupid when it comes
to "unusual" functionality. I guess you will find no tool supporting
your code even if it is possible map the functionlity in an ASIC
library. For a lot of techologies it is impossible to build your
described funtionlity using the given primitives.

bye Thomas


 
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backhus
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Posts: n/a
 
      04-01-2011
On 30 Mrz., 17:04, rickman <(E-Mail Removed)> wrote:
> On Mar 30, 8:49*am, Thomas Stanka <(E-Mail Removed)>
> wrote:
>
>
>
> > On 29 Mrz., 18:13, rickman <(E-Mail Removed)> wrote:

>
> > > I was using some logic to shorten typing of some operations where I
> > > was trying to create tristate drivers. *To be sure of the result I
> > > looked up the logic tables and found that, for example the OR function
> > > on a constant 'z' and a signal produces a '1' when the signal is a
> > > '1', but when the signal is a zero results in an 'x'. *This is not the
> > > same as a 'z' obviously, which is what I wanted. *Clearly this is not
> > > a good idea even if it is shorter to type.

>
> > So want the technology to contain a buffer that has an high impedance
> > output in case of one input is high impedance?
> > But else the output needs to be low impedance either driving '0' or
> > '1'. Seems quite unusual to be found in any tech library.

>
> > Your problems seems to me not vhdl related, instead you need to think
> > in dedicated hardware functionality.
> > It is quite easy to construct a logic function in vhdl that helps your
> > need for simulation purpose, but quite a hard job, to build the needed
> > transistor structure to implement the vhdl in real silicon.

>
> > best regards Thomas

>
> That's funny, I have some parts on a current board design that do
> pretty much this. *They are called switches. *One of the inputs will
> cause a 'Z' on the output when the input is a 'Z'. *A little logic
> added to the control input and it would do exactly what I was coding.
>
> Rick


Hi Rick,
if some input of a CMOS device really sees a 'Z' and does not use some
internal pullup,
it may end up oscillating at some very high frequency. In the worst
case this may even blow up your input buffer.

So if you have some board with switches that leave the inputs "open"
you are either required to use the internal pullups,
or there's some connector parallel to the switches so you can use the
I/Os for some other optional hardware (this requires the switches
always to be held in the open position).

In any case, a CMOS input will never properly recognize a 'Z'
condition, the input driver will either drive a '0' or '1'
and you can't establish a pure wire connection between two pads inside
an FPGA. There's always an IBUF and OBUF.

Have a nice synthesis
Eilert
 
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rickman
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Posts: n/a
 
      04-02-2011
On Apr 1, 3:47*am, backhus <(E-Mail Removed)> wrote:
> On 30 Mrz., 17:04, rickman <(E-Mail Removed)> wrote:
>
>
>
> > On Mar 30, 8:49*am, Thomas Stanka <(E-Mail Removed)>
> > wrote:

>
> > > On 29 Mrz., 18:13, rickman <(E-Mail Removed)> wrote:

>
> > > > I was using some logic to shorten typing of some operations where I
> > > > was trying to create tristate drivers. *To be sure of the result I
> > > > looked up the logic tables and found that, for example the OR function
> > > > on a constant 'z' and a signal produces a '1' when the signal is a
> > > > '1', but when the signal is a zero results in an 'x'. *This is not the
> > > > same as a 'z' obviously, which is what I wanted. *Clearly this isnot
> > > > a good idea even if it is shorter to type.

>
> > > So want the technology to contain a buffer that has an high impedance
> > > output in case of one input is high impedance?
> > > But else the output needs to be low impedance either driving '0' or
> > > '1'. Seems quite unusual to be found in any tech library.

>
> > > Your problems seems to me not vhdl related, instead you need to think
> > > in dedicated hardware functionality.
> > > It is quite easy to construct a logic function in vhdl that helps your
> > > need for simulation purpose, but quite a hard job, to build the needed
> > > transistor structure to implement the vhdl in real silicon.

>
> > > best regards Thomas

>
> > That's funny, I have some parts on a current board design that do
> > pretty much this. *They are called switches. *One of the inputs will
> > cause a 'Z' on the output when the input is a 'Z'. *A little logic
> > added to the control input and it would do exactly what I was coding.

>
> > Rick

>
> Hi Rick,
> if some input of a CMOS device really sees a 'Z' and does not use some
> internal pullup,
> it may end up oscillating at some very high frequency. In the worst
> case this may even blow up your input buffer.
>
> So if you have some board with switches that leave the inputs "open"
> you are either required to use the internal pullups,
> or there's some connector parallel to the switches so you can use the
> I/Os for some other optional hardware (this requires the switches
> always to be held in the open position).
>
> In any case, a CMOS input will never properly recognize a 'Z'
> condition, the input driver will either drive a '0' or '1'
> and you can't establish a pure wire connection between two pads inside
> an FPGA. There's always an IBUF and OBUF.
>
> Have a nice synthesis
> * Eilert


I think you are confusing two things. One is how synthesis works. It
concerns with the resulting overall behavior, it does not care how you
construct that behavior with your equations. The fact that I
propagate a 'z' through a logic block in the HDL does not require that
this block be replaced by some sort of gate that exactly implements
that block. This can easily be combined with whatever logic is
producing the 'z' that is to be propagated through the block and
result in a tristate driver with some logic function driving the
enable... which is exactly what I was trying to do.

The other point of confusion is how a switch works. A switch has a
logic input that operates as you describe and two switch I/Os that
literally operate as a passive switch. These I/Os will not oscillate
in any sense because they do not amplify.

This is all moot or as George Costanza might say, "moop". The logic
block does not propagate a 'z' and it is not worth writing my own
function for this.

Rick
 
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