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new in vhdl - a little question

ee1 ee1 is offline
Junior Member
Join Date: Mar 2011
Posts: 1
hey, i am new to vhdl, and i wrote a code for a register (the inpute size should be generic).
the register should have datain, enable, reset, and data out
my question is, how can i know if what i wrote works? i mean i compiled it and did not got errors, but how can i know if its functually works?
i uses modelsim.
here is my code:

library IEEE;
use IEEE.std_logic_1164.all;

entity register is
generic(DATA_WIDTH : integer := 8 );
port(clk, reset, load : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0));
end register;

architecture arc_register of register is
if (reset='1') then
data_out <=(others=>'0');
elsif(clk'event and clk='1')then
if(load = '1') then
end if;
end if;
end process;
end arc_register;

configuration cfg_register of register is
for arc_register
end for;
end cfg_register;

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rman123 rman123 is offline
Junior Member
Join Date: Mar 2011
Posts: 3
Google, "vhdl testbench" and read about it.
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