Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > counter help

Reply
Thread Tools

counter help

 
 
see-me see-me is offline
Junior Member
Join Date: Mar 2011
Posts: 4
 
      03-22-2011
i do my first programm in vhdl and i have a mistake and i dont know where it is..

i checked carefully all my work and i really dont know where am i wrong


please help me

HTML Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity counter is
  generic(G_DATA_WIDTH : integer := 8);
  port(clk,reset, load : in std_logic;
	   opcode : in std_logic_vector (1 downto 0);
       data_in : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
       cnt : out std_logic_vector(G_DATA_WIDTH-1 downto 0));
end counter;

architecture arc_counter of counter is
  SIGNAL temp1:   integer;
  signal ZEROS:  std_logic_vector(G_DATA_WIDTH-1 downto 0);
  signal ONES:   std_logic_vector(G_DATA_WIDTH-1 downto 0);
  
  
  
  

begin
  process(reset,clk)
    begin
  if( reset='1') then
    cnt <=(others =>'0');
  elsif reset='0' then
    if (clk'event and clk='1') then
   ONES <= (others => '1');
   ZEROS <= (others =>'0');
    temp1 <= to_integer(unsigned(cnt)); 
  
    cnt <=  std_logic_vector(to_unsigned(temp1+1,G_DATA_WIDTH))  when (opcode='01' and cnt/=ONES ),
             ZEROS     when opcode='01' and cnt=ONES , 
            std_logic_vector(to_unsigned(temp1-1,G_DATA_WIDTH))  when opcode='10' and cnt/=ZEROS  ,
            ONES                                         when opcode='10' and cnt=ZEROS  ,
            cnt                                          when opcode='00' ,                                          
            data_in when others ;
  end if;
end if;                                                                                              
end process; 
end arc_counter;

configuration cfg_counter of counter is
  for arc_counter
  end for;
end cfg_counter;
it wrote in the compiler the errors:

Cannot read output "cnt".

Illegal sequential statement.

counter.vhd(34): near ",": expecting ';'




 
Reply With Quote
 
 
 
 
joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
 
      03-22-2011
You are not allowed to 'read' the current cnt signal because it is an output signal.
You will have to introduce a help signal for it.

Also, you are not allowed to use this syntax inside a process:
Code:
val <=  a  when true,
           b when others;
Code:
architecture arc_counter of counter is
  SIGNAL temp1:   integer;
  signal ZEROS:  std_logic_vector(G_DATA_WIDTH-1 downto 0);
  signal ONES:   std_logic_vector(G_DATA_WIDTH-1 downto 0);
  
  cnt_curr : std_logic_vector(G_DATA_WIDTH-1 downto 0));
begin
  process(reset,clk)
    begin
  if( reset='1') then
    cnt_curr <=(others =>'0');
  elsif reset='0' then
    if (clk'event and clk='1') then
   ONES <= (others => '1');
   ZEROS <= (others =>'0');
    temp1 <= to_integer(unsigned(cnt)); 
  
    if (opcode='01' and cnt/=ONES ) then
      cnt_curr <=  std_logic_vector(to_unsigned(temp1+1,G_DATA_WIDTH));
    elsif ( opcode='01' and cnt_curr=ONES) then
       cnt_curr <=  ZEROS;
    elsif ( opcode='10' and cnt_curr/=ZEROS ) then
      cnt_curr <=  std_logic_vector(to_unsigned(temp1-1,G_DATA_WIDTH));
    elsif ( opcode='10' and cnt_curr=ZEROS ) then
      cnt_curr <=  ONES;
    elsif ( opcode='00'  ) then
      cnt_curr <= cnt_curr;
    else
      cnt_curr <= data_in;
    end if;
  end if;
end if;                                                                                              
end process; 

cnt <= cnt_curr;
end arc_counter;
 
Reply With Quote
 
 
 
 
see-me see-me is offline
Junior Member
Join Date: Mar 2011
Posts: 4
 
      03-23-2011
thanks very much i solvd the problems

now i am trying to do a test_banch for this counter

HTML Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;



entity shift_reg is
    PORT ( count : BUFFER bit_vector(8 downto 1));
end;

architecture only of shift_reg is
  
  constant GEN: integer := 8;


component counter 
  generic(G_DATA_WIDTH : integer := 8);
  port(clk,reset, load : in std_logic;
       opcode : in std_logic_vector (1 downto 0);
       data_in : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
       cnt : out std_logic_vector(G_DATA_WIDTH-1 downto 0));
end component;


SIGNAL clk1   : std_logic := '0';
SIGNAL reset1 : std_logic := '0';
SIGNAL load1 : std_logic := '0';
signal opcode1: std_logic_vector (1 downto 0);
signal  DATA1 :  std_logic_vector(GEN-1 downto 0);
signal  cnt1 :  std_logic_vector(GEN-1 downto 0);
begin

dut : counter 
  generic map (G_DATA_WIDTH => GEN);
   PORT MAP (clk => clk1,reset => reset1,load => load1,opcode => opcode1,data_in => DATA1,cnt => cnt1);

clock : PROCESS
   begin
     DATA1=1;
   opcode="01";
   wait for 10 ns; clk  <= not clk;
end PROCESS clock;

stimulus : PROCESS
   begin
   wait for 5 ns; reset  <= '1';
   wait for 4 ns; reset  <= '0';
   wait;
end PROCESS stimulus;


end only;
it wrote alot of errors like:

(vcom-1035) Formal port "clk" has OPEN or no actual associated with it.
(vcom-1035) Formal port "reset" has OPEN or no actual associated with it.
(vcom-1035) Formal port "load" has OPEN or no actual associated with it.
(vcom-1035) Formal port "opcode" has OPEN or no actual associated with it.
: (vcom-1035) Formal port "data_in" has OPEN or no actual associated with it.

near "PORT": syntax error

Illegal target for signal assignment.


i reallydont know where is the problem

i will be glad for help
thnaks in advance
 
Reply With Quote
 
joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
 
      03-24-2011
These are subtle mistakes...
I have to say the error messages your tool is giving aren't very clear.

GHDL gave these:
Code:
shift_reg.vhdl:35:4: unexpected token 'port' in a concurrent statement list
shift_reg.vhdl:39:11: "<=" or ":=" expected instead of =
shift_reg.vhdl:40:10: "<=" or ":=" expected instead of =
/usr/lib/ghdl/bin/ghdl: compilation error
There are two errors:

1. Don't put a semicolon after the generic map:
Code:
dut : counter 
  generic map (G_DATA_WIDTH => GEN)
   PORT MAP (clk => clk1,reset => reset1,load => load1,opcode => opcode1,data_in => DATA1,cnt => cnt1);
2. The other error lines should read like
Code:
--   DATA1<=1;
     opcode1<="01";
I'm not sure about that first line -- assigning an integer to a std_logic_vector seems strange, but I suppose it's allowed with the (non-standard) std_logic_arith library
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Page File counter and Private Bytes Counter George2 C++ 1 01-31-2008 09:27 AM
VHDL PULSE COUNTER - PLS HELP crazy_kuts VHDL 1 03-30-2006 06:50 PM
Session("counter") vs. ViewState("counter")...a newbie question The Eeediot ASP .Net 3 12-22-2004 09:31 PM
Counter help salman sheikh VHDL 2 01-07-2004 08:03 PM
BCD counter and 7 segment LCD help. bob VHDL 6 11-25-2003 05:30 PM



Advertisments