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VHDL: port mapping problems

HyroICED HyroICED is offline
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Join Date: Feb 2011
Posts: 1
I was wonderiing if anyone would be able to help me out with a problem i've been having with a VHDL module I have been working on.

This image shows what i'm working on its a multiplexer that takes 32 bits as input in the form of 4 input lines and an output of 8 bits, including 2 select lines. Now the code I have for this part works.
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Code for image above:

entity Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
end Multiplexer32to8;

architecture Behavioral of Multiplexer32to8 is

Signal A, B, C, D, Out_temp : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Wires used to create Input Array

Begin -- Main Body Begins

A <= DataStream (7 downto 0);
B <= DataStream (15 downto 8 );
C <= DataStream (23 downto 16);
D <= DataStream (31 downto 24);

process (A, B, C, D, SelectLine)
Case SelectLine is
when "00" => out_temp <= A;
when "01" => out_temp <= B;
when "10" => out_temp <= C;
when "11" => out_temp <= D;
when others => out_temp <= "ZZZZZZZZ"; -- Return Default added
end case;
end process;
ABCDOut <= out_temp;

end Behavioral;
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Now this next part is where I seem to be having trouble, I'm trying to create 6 copies of the component shown above using a long-about way of using generate. I have done a syntax check on this next bit of code and it's saying "Process "Check Syntax" completed successfully". But here is where the problem is because when I try to simulate this new code it doesn't work.


entity MultiplexerX6 is
Port ( DataStreams : in std_logic_vector(191 downto 0);
SelectLine : in std_logic_vector(11 downto 0);
ABCDEF: out std_logic_vector(5 downto 0));
end MultiplexerX6;

architecture Structural of MultiplexerX6 is

component Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
end component;

signal A_temp, B_temp, C_temp, D_temp, E_temp, F_temp : std_logic_vector(31 downto 0);
signal OutA_temp, OutB_temp, OutC_temp, OutD_temp, OutE_temp, OutF_temp : std_logic_vector(7 downto 0);


A_temp <= DataStreams (31 downto 0);
B_temp <= DataStreams (63 downto 32);
C_temp <= DataStreams (95 downto 64);
D_temp <= DataStreams (127 downto 96);
E_temp <= DataStreams (159 downto 128 );
F_temp <= DataStreams (191 downto 160);

B1: Multiplexer32to8 port map(A_temp, SelectLine(1 DOWNTO 0), OutA_temp);
B2: Multiplexer32to8 port map(B_temp, SelectLine(3 DOWNTO 2), OutB_temp);
B3: Multiplexer32to8 port map(C_temp, SelectLine(5 DOWNTO 4), OutC_temp);
B4: Multiplexer32to8 port map(D_temp, SelectLine(7 DOWNTO 6), OutD_temp);
B5: Multiplexer32to8 port map(E_temp, SelectLine(9 DOWNTO 8 ), OutE_temp);
B6: Multiplexer32to8 port map(F_temp, SelectLine(11 DOWNTO 10), OutF_temp);

OutALL_TEMP(0)<= OutA_temp(0) and OutA_temp(1) AND OutA_temp(2) and OutA_temp(3) and OutA_temp(4) AND OutA_temp(5) and OutA_temp(6) AND OutA_temp(7);
OutALL_TEMP(1)<= OutB_temp(0) and OutB_temp(1) AND OutB_temp(2) and OutB_temp(3) and OutB_temp(4) AND OutB_temp(5) and OutB_temp(6) AND OutB_temp(7);
OutALL_TEMP(2)<= OutC_temp(0) and OutC_temp(1) AND OutC_temp(2) and OutC_temp(3) and OutC_temp(4) AND OutC_temp(5) and OutC_temp(6) AND OutC_temp(7);
OutALL_TEMP(3)<= OutD_temp(0) and OutD_temp(1) AND OutD_temp(2) and OutD_temp(3) and OutD_temp(4) AND OutD_temp(5) and OutD_temp(6) AND OutD_temp(7);
OutALL_TEMP(4)<= OutE_temp(0) and OutE_temp(1) AND OutE_temp(2) and OutE_temp(3) and OutE_temp(4) AND OutE_temp(5) and OutE_temp(6) AND OutE_temp(7);
OutALL_TEMP(5)<= OutF_temp(0) and OutF_temp(1) AND OutF_temp(2) and OutF_temp(3) and OutF_temp(4) AND OutF_temp(5) and OutF_temp(6) AND OutF_temp(7);


end Structural;
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I'd be very greatful if anyone could help me out with this problem I'm having.

Also This VHDL Module doesn't show up in the Implementation Source window, and can only be seen in the Behavioral Simulation window, so not allowing me to run simulation.

Last edited by HyroICED; 03-21-2011 at 01:13 PM.. Reason: MORE TO ADD
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