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Weird XST error initializing record type on reset

 
 
Don Otknow
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      03-10-2011
Hello,

I just had an odd error with XST. I have a record and code to
initialize it in a process:

architecture behavioral of vectors is

type six_vectors is record
vect_a : std_logic_vector(15 DOWNTO 0);
vect_b : std_logic_vector(15 DOWNTO 0);
vect_c : std_logic_vector(15 DOWNTO 0);
vect_d : std_logic_vector(15 DOWNTO 0);
vect_e : std_logic_vector(15 DOWNTO 0);
vect_f : std_logic_vector(15 DOWNTO 0);
end record;

signal six_vect_inst : six_vectors;

begin

some_process : process(rst,clk)
begin
if rst = '1' then
six_vect_inst <= (others => (others => '0'));
elsif clk'event and clk='1' then
do_some_stuff
end if;
end process;

end behavioral;

This doesn't work. XST gives me:

FATAL_ERROR:Simulator:CompilerAssert.h:40:1.64.18. 3.18.1 - Internal
Compiler Error in file ../src/VhdlExpr.cpp at line 2582 Process will
terminate.

I read in a related error report on a Xilinx site that user-defined
types would cause ISE 12.1 to throw these types of errors. So I
changed the code to:

some_process : process(rst,clk)
begin
if rst = '1' then
six_vect_inst.vect_a <= (others => '0');
six_vect_inst.vect_b <= (others => '0');
six_vect_inst.vect_c <= (others => '0');
six_vect_inst.vect_d <= (others => '0');
six_vect_inst.vect_e <= (others => '0');
six_vect_inst.vect_f <= (others => '0');
elsif clk'event and clk='1' then
do_some_stuff
end if;
end process;

and it worked fine. Does anyone have any insight into why these cases
are handled so differently?
 
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westocl westocl is offline
Junior Member
Join Date: Mar 2011
Posts: 4
 
      03-11-2011
I don't use record types much because I havent seen much benefit to them except for maybe code clarity, so i am not positive about the syntax, but it looks like

six_vect_inst <= (others => (others => '0'));

you are trying to assign all zeros to each element in the record as if it were an array of logic vectors which it is not, so im not sure VHDL language will let you do it, and it is not necessarily an XST issue its a VHDL syntax issue.

six_vect_inst.vect_a <= (others => '0');
six_vect_inst.vect_b <= (others => '0');
six_vect_inst.vect_c <= (others => '0');
six_vect_inst.vect_d <= (others => '0');
six_vect_inst.vect_e <= (others => '0');
six_vect_inst.vect_f <= (others => '0');

is syntactical correct as you assign each element of the record separately, so you can run with it, but you loose what you origionally intended to do, in grouping signals together.


A record is really only useful if you were to have vectors of different size and wanted to 'group' them for clarity., in the case you presented, you want to use an array of logic vector.

hope this helps
 
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Bart Fox
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      03-11-2011
Am 11.03.11 00:41, schrieb Don Otknow:
> and it worked fine. Does anyone have any insight into why these cases
> are handled so differently?

I think the "(others => (others =>" works only for arrays like:
type six_vectors is array(0 to 5) of : std_logic_vector(15 DOWNTO 0);

For records I define an default constant beside:

constant default_six_vectors: six_vectors := (
vect_a => (others => '0'),
vect_b => (others => '0'),
vect_c => (others => '0'),
vect_d => (others => '0'),
vect_e => (others => '0'),
vect_f => (others => '0')
);

You can use this default constant in your reset path.
And you can easily mix diffrent data types in your record.
Also you can never forget to reset an value in this record if you use
the constant. The compiler will complain if the default constant is not
complete.

regards
Bart
 
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Bart Fox
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      03-16-2011
Am 12.03.11 00:47, schrieb Alan Fitch:
> On 11/03/11 05:34, Bart Fox wrote:
>> Am 11.03.11 00:41, schrieb Don Otknow:
>>> and it worked fine. Does anyone have any insight into why these cases
>>> are handled so differently?

>> I think the "(others => (others =>" works only for arrays like:
>> type six_vectors is array(0 to 5) of : std_logic_vector(15 DOWNTO 0);

> Perhaps surprisingly, others is allowed for records: here's a quote from

Thanks for pointing that out.
This seems to be another one on my list: What XST should do, but it fails.

regards
Bart
 
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Bart Fox
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Posts: n/a
 
      03-18-2011
Am 11.03.11 00:41, schrieb Don Otknow:
> This doesn't work. XST gives me:
>
> FATAL_ERROR:Simulator:CompilerAssert.h:40:1.64.18. 3.18.1 - Internal
> Compiler Error in file ../src/VhdlExpr.cpp at line 2582 Process will
> terminate.

Ok, I have checked this case:
Modelsim (6.5) do it right, XST (12.2) do it right, the problem is only
ISIM, the simulator....

regards,
Bart
 
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