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Hi,
The IEEE VHDL Analysis and Standardization Group (VASG)
is in the preliminary stages of discussing items to be
considered for the next VHDL standard.

Anyone with a vested interest in VHDL is welcome to join
the reflector and either observe or participate in the discussion.
I would particularly encourage all experienced VHDL design and
verification engineers to join.

To join the working group reflector, see the following link:
http://www.eda.org/vasg/index.html#Participation

_Next Meeting_: Thursday March 3 at 8 am Pacific
This is a phone conference. See reflector for dial-in details.

_Homework_ due Thursday March 3:
Post your change requirement list to the reflector.

_minutes from previous meetings are here_:
http://www.eda.org/vasg/meetings/

Best,
Jim Lewis
VHDL Study Group Chair