hello

I am writing a code in vhdl for line tracker sensor and according to a design a made ( the pictures are attached)

I am sure this isnt the way to implement a a/d and I am looking for a better way to do that.

keeping in mind that the input from the sensor could change between 0 - 3.3 [volt] and let say that from 1.3 it's consider to be '1'

the code I wrote

Code:

library IEEE;
use ieee.std_logic_1164.all;
entity Line_tracker is
-- generic ( black: std_logic := 1;
-- white: std_logic := '0'
-- );
port (
data_left: in std_logic;
data_right: in std_logic;
Clk: in std_logic;
Reset: in std_logic;
Enable: in std_logic;
error_left: out std_logic;
error_right:out std_logic
);
end entity Line_Tracker;
architecture arc_Line_Tracker of Line_Tracker is
signal l_dataout: std_logic;
signal l_high_bit: std_logic;
signal l_low_bit: std_logic;
signal l_reg: std_logic;
signal r_dataout: std_logic;
signal r_high_bit: std_logic;
signal r_low_bit: std_logic;
signal r_reg: std_logic;
begin
left_reg: process (Clk,Reset,Enable)
begin
if (Reset = '0') then
l_dataout <= '0';
l_high_bit <= '0';
l_low_bit <= '0';
error_left <= '0';
l_reg <= '0';
elsif rising_edge(Clk) and (Enable = '1') then
l_dataout <= data_left;
if (l_dataout = '1') then
l_high_bit <= '1';
l_low_bit <= '0';
else
l_high_bit <= '0';
l_low_bit <= '1';
end if;
if ((l_high_bit and (not l_low_bit)) = '1' ) then
l_reg <= '1';
end if;
error_left <= l_reg;
end if;
end process left_reg;
right_reg: process (Clk,Reset,Enable)
begin
if (Reset = '0') then
r_dataout <= '0';
r_high_bit <= '0';
r_low_bit <= '0';
error_right <= '0';
r_reg <= '0';
elsif rising_edge(Clk) and (Enable = '1') then
r_dataout <= data_right;
if (r_dataout = '1') then
r_high_bit <= '1';
r_low_bit <= '0';
else
r_high_bit <= '0';
r_low_bit <= '1';
end if;
if ((r_high_bit and (not r_low_bit)) = '1') then
r_reg <= '1';
end if;
error_right <= r_reg;
end if;
end process right_reg;
end architecture arc_Line_Tracker;

thanks in advance