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Identifier "adder" does not identify a component declaration.

anagarwal89 anagarwal89 is offline
Junior Member
Join Date: Jan 2011
Posts: 1
When I compile my code for a 32 bit adder, I get this error. My code for adder is compiling successfully but testbench is giving error.
Here's my code for testbench:
library ieee;
use ieee.std_logic_1164.all;

entity adder_testbench is
end adder_testbench;

architecture behavior of adder_testbench is

signal a_tb: std_logic_vector(31 downto 0);
signal b_tb: std_logic_vector(31 downto 0);
signal sum_tb: std_logic_vector(31 downto 0);
signal co_tb :std_logic ;
signal cin_tb : std_logic;
component adder
port (A,B: in std_logic_vector(31 downto 0);
CIN: in std_logic;
S: out std_logic_vector(31 downto 0);
COUT: out std_logic);
end component;
uut: Work.adder port map(A => a_tb, B => b_tb, CIN => cin_tb, S => sum_tb, COUT => co_tb);

tb1: process
constant period1: time := 20ns;
a_tb<= "00000000000000001111111111111111";
b_tb<= "11111111111111110000000000000000";
cin_tb<= '0';

wait for period1;

assert ((sum_tb = "11111111111111111111111111111111") and (co_tb ='0'))
report "test failed for combination" severity error;

end process tb1;
end behavior;
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joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
Uhm perhaps you need to leave out the Work prefix:
uut: adder port map(A => a_tb, B => b_tb, CIN => cin_tb, S => sum_tb, COUT => co_tb);
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Philippe.Faes Philippe.Faes is offline
Junior Member
Join Date: Jan 2011
Posts: 4
You can either write:

uut: adder port map( ...

which will instantiate the component you have typed in the declarative part of your architecture, or you can write:

uut: entity work.adder port map( ...

Which will directly instantiate the entity. No need to copy the component declaration if you use this style.

You can even specify which architecture you want:

uut: entity work.adder(RTL) port map( ...

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