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lccwin fails to generate NOPs

 
 
Keith Thompson
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      01-04-2011
Edward Rutherford <(E-Mail Removed)> writes:
> Ben Pfaff wrote:
>> jacob navia <(E-Mail Removed)> writes:
>>
>>> Le 04/01/11 23:30, Edward Rutherford a écrit :
>>>> I am trying to write code that includes a certain number of NOPs in
>>>> the generated machine code, I would like to do it portably so without
>>>> using inline asm.
>>>
>>> I can develop a special version FOR YOU that will emit a NOP when you
>>> write an empty statemnt.

>>
>> A special version of lcc-win will not be a portable solution.

>
> True - perhaps C needs a new nop keyword to be added.


Ok, I'll ask. Why would this be useful?

[...]

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Keith Thompson (The_Other_Keith) http://www.velocityreviews.com/forums/(E-Mail Removed) <http://www.ghoti.net/~kst>
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BartC
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      01-04-2011


"Edward Rutherford" <(E-Mail Removed)> wrote in
message news:ig072m$j1q$(E-Mail Removed)...

> I am trying to write code that includes a certain number of NOPs in the
> generated machine code, I would like to do it portably so without using
> inline asm.


I'm not sure the concept of Nop is even portable...

Did you have a particular machine instruction in mind, for every conceivable
machine? If not then it probably doesn't matter what instructions are
generated; maybe you can even use some actual C code.

--
Bartc

 
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glen herrmannsfeldt
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      01-04-2011
In comp.compilers.lcc BartC <(E-Mail Removed)> wrote:
(snip)

> I'm not sure the concept of Nop is even portable...


Some machines have more than one...

> Did you have a particular machine instruction in mind, for every conceivable
> machine? If not then it probably doesn't matter what instructions are
> generated; maybe you can even use some actual C code.


The favorite problem when writing benchmarks, of making sure that
the compiler doesn't optimize away the operations. How about

i += 0;

i *= 1;

i /= 1;

with no optimization, how many compilers will generate the
specified operation?

-- glen

 
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BartC
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      01-04-2011
"glen herrmannsfeldt" <(E-Mail Removed)> wrote in message
news:ig0adc$ob0$(E-Mail Removed)-september.org...
> In comp.compilers.lcc BartC <(E-Mail Removed)> wrote:


>> Did you have a particular machine instruction in mind, for every
>> conceivable
>> machine? If not then it probably doesn't matter what instructions are
>> generated; maybe you can even use some actual C code.

>
> The favorite problem when writing benchmarks, of making sure that
> the compiler doesn't optimize away the operations. How about
>
> i += 0;
>
> i *= 1;
>
> i /= 1;
>
> with no optimization, how many compilers will generate the
> specified operation?


I was going to say my compiler, but I've just tried it, and no code! (A bit
of a surprise because I thought it did no useful optimisations at all, let
alone for silly, unlikely code.)

But it does generate code for:

i;

It would be difficult I think to find a C expression that doesn't access
memory, sets no flags, generates a single byte of code, and behaves
consistently across machines; but depending on exactly why these no-ops are
needed, that may or may not be important.

--
Bartc

 
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Ben Pfaff
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      01-05-2011
"BartC" <(E-Mail Removed)> writes:

> It would be difficult I think to find a C expression that doesn't
> access memory, sets no flags, generates a single byte of code, and
> behaves consistently across machines; but depending on exactly why
> these no-ops are needed, that may or may not be important.


The "single byte of code" part is impossible, because some
architectures have fixed-length instructions that are wider than
one byte.
--
Ben Pfaff
http://benpfaff.org
 
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glen herrmannsfeldt
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      01-05-2011
In comp.compilers.lcc Ben Pfaff <(E-Mail Removed)> wrote:
> "BartC" <(E-Mail Removed)> writes:


>> It would be difficult I think to find a C expression that doesn't
>> access memory, sets no flags, generates a single byte of code, and
>> behaves consistently across machines; but depending on exactly why
>> these no-ops are needed, that may or may not be important.


> The "single byte of code" part is impossible, because some
> architectures have fixed-length instructions that are wider than
> one byte.


For IA32 the NOP instruction, X'90', is in the position where

XCHG AX,AX

would be, and presumably is generated for that case.

The only other one that I happen to remember is for S/360
(and successors), where there is a four byte NOP, and two
byte NOPR. (That is, RX form and RR form.) Those are the
two forms of conditional branch with the mask set to zero.
They have an operand which is an address (RX), or register (RR).

-- glen
 
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robertwessel2@yahoo.com
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      01-05-2011
On Jan 4, 6:19*pm, glen herrmannsfeldt <(E-Mail Removed)> wrote:
> In comp.compilers.lcc Ben Pfaff <(E-Mail Removed)> wrote:
>
> > "BartC" <(E-Mail Removed)> writes:
> >> It would be difficult I think to find a C expression that doesn't
> >> access memory, sets no flags, generates a single byte of code, and
> >> behaves consistently across machines; but depending on exactly why
> >> these no-ops are needed, that may or may not be important.

> > The "single byte of code" part is impossible, because some
> > architectures have fixed-length instructions that are wider than
> > one byte.

>
> For IA32 the NOP instruction, X'90', is in the position where
>
> * XCHG AX,AX
>
> would be, and presumably is generated for that case.



These days Intel defines single instruction x86 NOPs from 1 to 9 bytes
in length. The longer forms actually code memory references, but are
guaranteed not to actually access that memory.


> The only other one that I happen to remember is for S/360
> (and successors), where there is a four byte NOP, and two
> byte NOPR. *(That is, RX form and RR form.) *Those are the
> two forms of conditional branch with the mask set to zero.
> They have an operand which is an address (RX), or register (RR).



These days you can code a Branch Relative Condition Long, and get a
six byte NOP.

What does it say about the longevity of ISAs when the architects have
found time define additional no-operation instructions?

In the same vein, both Intel and IBM have defined explicit undefined
instructions. Intel even gave it a mnemonic.
 
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glen herrmannsfeldt
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      01-05-2011
In comp.compilers.lcc (E-Mail Removed) <(E-Mail Removed)> wrote:
(snip, I wrote)

>> For IA32 the NOP instruction, X'90', is in the position where


>> * XCHG AX,AX


>> would be, and presumably is generated for that case.


> These days Intel defines single instruction x86 NOPs from 1 to 9 bytes
> in length. The longer forms actually code memory references, but are
> guaranteed not to actually access that memory.


Hmm, my book doesn't have those. Well, I use the IA32 part of
the Itanium reference as an IA32 reference. It should be right, though.

(snip on S/360 NOP and NOPR)

> These days you can code a Branch Relative Condition Long, and get a
> six byte NOP.


It seems that there is now JNOP and JLNOP as assembler mnemonics
for not branching with BRC and BRCL. Note that all four have an
operand, though it could be zero if not otherwise needed.

Then there is the PDP-10. I am not sure which instruction is
the official NOP, but there are the JUMP and SKIP with the
descriptions "Don't JUMP" and "Don't SKIP", respectively.

> What does it say about the longevity of ISAs when the architects have
> found time define additional no-operation instructions?


> In the same vein, both Intel and IBM have defined explicit undefined
> instructions. Intel even gave it a mnemonic.


and IBM has the DIAGNOSE instruction, specificially implementation
dependent, and with no mnemonic defined. As it used with VM,
I believe that there is an assembler macro to generate one.

-- glen
 
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robertwessel2@yahoo.com
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      01-05-2011
On Jan 4, 11:12*pm, glen herrmannsfeldt <(E-Mail Removed)> wrote:
> In comp.compilers.lcc (E-Mail Removed) <(E-Mail Removed)> wrote:
> (snip, I wrote)
> and IBM has the DIAGNOSE instruction, specificially implementation
> dependent, and with no mnemonic defined. *As it used with VM,
> I believe that there is an assembler macro to generate one.



"DIAG" actually. A problem for the assembler is that Diagnose doesn't
even have a defined format. VM's usage is RS, but other than being a
four byte instruction, nothing defined at the hardware level. And I
don't think the macro is there in VSE or MVS, or at least it didn't
used to be there. Our supervisor mode code that issues Diagnoses to
VM from supervisor mode in those OS's uses our own macro (although
that's been that either been unchanged or copied from old code for the
last couple of decades).
 
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BartC
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      01-05-2011
"glen herrmannsfeldt" <(E-Mail Removed)> wrote in message
news:ig0ukn$c16$(E-Mail Removed)-september.org...

> Then there is the PDP-10.


Not exactly common these days...

I am not sure which instruction is
> the official NOP, but there are the JUMP and SKIP with the
> descriptions "Don't JUMP" and "Don't SKIP", respectively.


There was SKIPN and (iirc) JUMPN. SKIPN did seem a bit pointless, but it was
just a consequence of a particular pattern of condition codes.

In the same way many processors will have the apparently pointless
instructions MOV Rn,Rn, or EXCH Rn,Rn, otherwise there would be an untidy
hole in the opcode map.

As I said, there are various ways of constructing a no-op instruction, so
which one should be generated from an empty C statement? (Although this is
the first I've heard of such a statement having to generate a NOP
instruction.)

--
Bartc

 
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