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VHDL Automated Testing

 
 
Paul Uiterlinden
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      12-28-2010
JimLewis wrote:

> turn on VHDL-2008 and use:
> std.env.stop(2) ;
>
> The intent is that the integer parameter is
> returned to the calling program. Not sure
> how the simulators are implementing it, but
> if it does not work like you expect, submit a
> bug report against it.


In ModelSim it has been implemented as:

For both STOP and FINISH the STATUS values are those used
in the Verilog $finish task
0 prints nothing
1 prints simulation time and location
2 prints simulation time, location, and statistics about
the memory and CPU times used in simulation

Other STATUS values are interpreted as 0.

--
Paul Uiterlinden
www.aimvalley.nl
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