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[Testing Test]

Hi,

The following piece of Verilog code is causing some problem. It's compiling fine in ModelSim but when run, it doesn't stop. Probably there might be some problem with the loops. Please go through the code and suggest any possible solutions.

Thank you.

Source Code (File Name: Mix_Col.v)

module Mix_Col(MC,SR);
    output [127:0]MC;
    input [127:0]SR;
    reg [127:0]MC;
    reg [7:0]tempSR[3:0][3:0];
    reg [7:0]tempMC[3:0][3:0];
    reg [1:0]Multiplier_Matrix[3:0][3:0];
    reg [1:0]k,n,o,j,i;
    reg [7:0]Transformed_Value,Variable;
    reg temp,m;
    initial
    begin
        Multiplier_Matrix[0][0]=2'b10;
        Multiplier_Matrix[0][1]=2'b11;
        Multiplier_Matrix[0][2]=2'b01;
        Multiplier_Matrix[0][3]=2'b01;
        Multiplier_Matrix[1][0]=2'b01;
        Multiplier_Matrix[1][1]=2'b10;
        Multiplier_Matrix[1][2]=2'b11;
        Multiplier_Matrix[1][3]=2'b01;
        Multiplier_Matrix[2][0]=2'b01;
        Multiplier_Matrix[2][1]=2'b01;
        Multiplier_Matrix[2][2]=2'b10;
        Multiplier_Matrix[2][3]=2'b11;
        Multiplier_Matrix[3][0]=2'b11;
        Multiplier_Matrix[3][1]=2'b01;
        Multiplier_Matrix[3][2]=2'b01;
        Multiplier_Matrix[3][3]=2'b10;
        k=2'b00;
        n=2'b00;
        temp=1'b0;
        Transformed_Value=8'd0;
        Variable=8'd0;
    end
    always@(SR)
    begin
        tempSR[0][0]=SR[127:120];
        tempSR[0][1]=SR[119:112];
        tempSR[0][2]=SR[111:104];
        tempSR[0][3]=SR[103:96];
        tempSR[1][0]=SR[95:88];
        tempSR[1][1]=SR[87:80];
        tempSR[1][2]=SR[79:72];
        tempSR[1][3]=SR[71:64];
        tempSR[2][0]=SR[63:56];
        tempSR[2][1]=SR[55:48];
        tempSR[2][2]=SR[47:40];
        tempSR[2][3]=SR[39:32];
        tempSR[3][0]=SR[31:24];
        tempSR[3][1]=SR[23:16];
        tempSR[3][2]=SR[15:8];
        tempSR[3][3]=SR[7:0];  
       for (o=0;o<=3;o=o+1)
       begin
           for (j=0;j<=3;j=j+1)
           begin
               for (i=0;i<=3;i=i+1)
               begin
                   for (m=0;m<=1;m=m+1)
                   begin
                       if (m==0)
                       begin
                           Transformed_Value=tempSR[o][i];
                       end
                       else
                       begin
                           temp=Transformed_Value[7];
                           Transformed_Value=Transformed_Value<<1;
                       end
                       if (temp==1'b1)
                       begin
                           Transformed_Value=Transformed_Value^8'h1b;
                           temp=1'b0;
                       end
                       if (Multiplier_Matrix[k][n][m]==1)
                       begin
                           Variable=Variable^Transformed_Value;
                       end
                   end
                   n=n+1;
               end
               tempMC[o][j]=Variable;
               Variable=8'd0;
               k=k+1;
               n=2'b00;
           end
           k=2'b00;
       end
       MC={tempMC[0][0],tempMC[0][1],tempMC[0][2],tempMC[0][3],tempMC[1][0],tempMC[1][1],tempMC[1][2],tempMC[1][3],tempMC[2][0],tempMC[2][1],tempMC[2][2],tempMC[2][3],tempMC[3][0],tempMC[3][1],tempMC[3][2],tempMC[3][3]};
   end
endmodule

Stimulus (File Name: Stim_Mix_Col.v)

module Stim_Mix_Col();
    wire [127:0]MC;
    reg [127:0]SR;
    Mix_Col M1(MC,SR);
    initial
    begin
        SR=128'h876e46a6f24ce78c4d904ad897ecc395;
 end
 endmodule