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entire 32 bit two's complement integer range is supported in VHDL?

 
 
c.d.b.meis c.d.b.meis is offline
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Join Date: Oct 2010
Posts: 1
 
      10-26-2010
Hi everybody,
I'm designing a VHDL testbench for a VHDL module.

I have to generate values to be written into a 32 bit register of my
module.
I decided tu use integer variables to compose my data and than convert them
to std_logic_vector to perform the write operation on the module.

The issue is that I discovered that VHDL
integer range is from -2147483647 to 2147483647,
that is to say 16#80000000# integer is not supported.

Is there any way to work out this limitation without using directly
std_logic_vector type?

Thank you in advance for any help

Claudia
 
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