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type casting / conversion again

 
 
Jonathan Bromley
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      10-22-2010
On Oct 22, 12:33*pm, rickman <gnu...@gmail.com> wrote:
> I believe the original version is not only ugly (the woes of VHDL type
> conversions), but it is wrong. *Shouldn't part of this be
> acc(acc'length-1 downto acc'length-1) ?


Yes - good catch. Sorry.

> I normally use name'high in this context. *
> But considering 'high vs. 'left, I wouldn't
> know where the trade-offs are. *I guess 'high may
> not be correct if numbered 0..N which is possible.
>*'left would not work if the msb is not left, but
> that wouldn't be compatible with unsigned would it?


Yes, the MSB is always 'left and I probably should have
used that. However, there's still another potential
goof because when writing
acc(acc'left downto acc'left)
you need to choose "to" or "downto" based on the original
declaration of acc. However, if you get that wrong the compiler
will pick it up.

I wish it were possible to declare unconstrained arrays
in VHDL with the to/downto direction constrained:

type jonathans_unsigned is array(natural range >) of ...

(where "range <>" allows both to/downto, "range >" allows
only downto, "range <" allows only to) so that it would
then be illegal to declare any jonathans_unsigned with
a "to" direction. But it is not so

The standard defence against being given an array that
might have inappropriate direction is to copy or alias
it onto an array whose subscript range you've normalized.
I'm pretty paranoid about always doing that in real code,
but I got sloppy in this morning's post.

Thanks

Jonathan

 
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