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Generate component

 
 
kmponis kmponis is offline
Junior Member
Join Date: Sep 2010
Posts: 3
 
      09-29-2010
Helloooo

I would like to know if i can generate an entity into a process ?

Im doing this :

PROCESS
BEGIN

gen_modul: for j in 0 to 63 loop

d_mem : d_mem_131072x16 PORT MAP (clk,"0000000000000000",addr,'0',d_mem_out);


end loop gen_modul;

END PROCESS;


And I have an ERROR : parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
 
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joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
 
      09-29-2010
Uhmm no you can't do this inside a process.
Though you can use for-generate and if-generate;


constant zero : std_logic_vector(15 downto 0) := (others => '0');

gen_modul: for j in 0 to 63 generate
d_mem : d_mem_131072x16 PORT MAP (clk,zero,addr,zero(0),d_mem_out);
end generate gen_modul;
 
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kmponis kmponis is offline
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Join Date: Sep 2010
Posts: 3
 
      10-01-2010
Thanks Joris thats working !!

Actually i want to read continueing blocks of the memory and edit the prices im getting !!

Can you help me with this because i think with generate loop i cant do something like this !
 
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joris joris is offline
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Join Date: Jan 2009
Posts: 152
 
      10-01-2010
Uhm can't you do this inside a process to handle the results you got from the memory component ? The process should probably be clocked as the memory is as well.
 
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