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Simple state-machine problem (how to memoriza inside process)

Carlos Carlos is offline
Junior Member
Join Date: Sep 2010
Posts: 1

I'm trying to make a state-machine wich remains in one of the states until one of the variables goes from zero to one three times. I assume it should be quite simple, but after some days I can't succeed. I have tried to save the number of changes both in variables and signals, but no result.

To make a simple test, I just made one simple state-machine with two states. It remains on the first one till the signal_to_monitor =1. Then it goes to second state and the idea is to get out of that state after three transitions 0-1 of the signal we are monitoring.

The code used is:

architecture ctrl_machine of machine is

type possible_states is (first_st,second_st);
signal next_state,state: possibles_states;
signal accumulate : integer range 0 to 5;


RefreshState : process (clk,reset)
if (reset='1') then
estat <= idle;
elsif (clk'event and clk='1') then
estat <= seguent_estat;
end if;
end process RefreshState;

NextState rocess (state,signal_to_monitor)

next_state <= state;
case state is

when first_st =>

if (signal_to_monitor ='1') then
next_state <= second_st;
accumulate <=0;
next_state <= first_st;
end if;

when second_st =>
next_state <= buidant_calaix;
if (signal_to_monitor = '1') then
accumulate <=accumulate +1;
end if;
if (accumulate = 3) then
end if;
end case;
end process;

output_proc: process (state)

case (state) is
when first_st => output <='0';
when second_st => output <='1';

end case;
end process ;


I assume it should be a conceptual error but can't find it! The signal (accumulate) gets mad and begins to flip-flop without control (suppose due to accumulate=accumulate+1 but don't know how to accomplish this simple goal!).

Any ideas?


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jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
Hi Carlos

You could use a two-bit shiftregister in order to detect 0->1 shift of the "signal_to_monitor".

It should be done like this.

signal Shiftreg: std_logic_vector( 1 downto 0) := "00";

Shiftreg <= Shiftreg[0] & signal_to_monitor;

if Shiftreg="01" then
accumulate <=accumulate +1;
...... and so on

Your welcome
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