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VHDL - parameterised generic constants

 
 
janeruth janeruth is offline
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Join Date: Jul 2009
Posts: 9
 
      07-29-2010
Hi,

Wondering if someone can shed some light for me.

A very simple version of my problem code is effectively:

entity
...
generic (ID : std_logic_vector (3 downto 0):= "1101")
....
architecture

signal sigX : std_logic_vector (5 downto 0);
...
begin

with sigX select
portY <= "101" when "11"&ID,
"110" when "00"&"----",
"000" when others;
...

Syntax check is fine but on synthesis I'm warned that portY isn't used. I've narrowed the problem down to the fact that the condition includes the generic ID and if I make ID a constant my problem goes away.

However, the whole point for me is to use the generic as a parameter such that multiple instances of this module will have different ID values which can be assigned individually with a 'for generate'.

For the case of one module on its own, the ID isn't going to change and is therefore effectively a constant so the synthesizer shouldn't have a problem but how do i go about assuring it that this is the case. Putting the keyword constant into the generic declaration doesn't help.

...?

Much thanks for any help!
 
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janeruth janeruth is offline
Junior Member
Join Date: Jul 2009
Posts: 9
 
      07-29-2010
For what it's worth; I've fixed the problem by changing from with-select to a when-else statement. Although I am still mystified as to why that should solve things, or why I even had a problem to start with as the generic should effectively be treated as a constant.

Either way, in case anyone with a similar issue finds this, that was my solution. However, I am now worried about the difference between with-select and when-else. As best as I know when-else enforces a priority on the ordering but would appreciate any other clarification.
 
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