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How to run simulation in Xilinx 12.1 ISE

 
 
udayjayachandran udayjayachandran is offline
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Join Date: Jul 2010
Posts: 6
 
      07-15-2010
Hi,
I have multiple seperate VHD files for a CPU. How can i run all the files and simulate the design to see the results. Can anyone help me. I have included all files by using add source option. But frm then i dont know how to proceed.



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Thanks,
UDAY
 
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jeppe jeppe is offline
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Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      07-16-2010
Your multiple VHDL files must be used to form one large design - otherwise can't they be simulated together.

Use structural VHDL or draw a Schematic with your component (VHDL files/modules)
 
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