Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > How to run simulation in Xilinx 12.1 ISE

Thread Tools

How to run simulation in Xilinx 12.1 ISE

udayjayachandran udayjayachandran is offline
Junior Member
Join Date: Jul 2010
Posts: 6
I have multiple seperate VHD files for a CPU. How can i run all the files and simulate the design to see the results. Can anyone help me. I have included all files by using add source option. But frm then i dont know how to proceed.

Reply With Quote
jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
Your multiple VHDL files must be used to form one large design - otherwise can't they be simulated together.

Use structural VHDL or draw a Schematic with your component (VHDL files/modules)
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Re: How include a large array? Edward A. Falk C Programming 1 04-04-2013 08:07 PM
Error in FIFO Simulation ISE Xilinx nfirtaps VHDL 1 08-31-2006 05:17 PM
Xilinx ISE schematic design Sleep Mode VHDL 0 05-04-2004 07:41 PM
Error message in Mapping while using Xilinx ISE 6.1.03i Sachin VHDL 1 01-30-2004 03:32 PM
FFT using Xilinx ISE Hari VHDL 1 01-05-2004 04:35 PM