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sfixed in generics

 
 
Paul
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      07-08-2010
Hi,

in the example attached I did try to parametrize my fir filter (direct
form I second order structure) internal signals. Modelsim complains on
it and I have no idea why and how to fix it. Anyway, the idea behind
should be clear.

Thanks,
Olaf


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library floatfixlib;
use floatfixlib.math_utility_pkg.all; -- ieee_proposed for VHDL-93 version
use floatfixlib.fixed_pkg.all; -- ieee_proposed for compatibility version

entity df1tsos is

generic(
numerator: sfixed := sfixed(16 downto -14); -- [-2 2)
denominator: sfixed := sfixed(16 downto -14); -- [-2 2)
numerator_state: sfixed := sfixed(16 downto -12); -- [-8
denominator_state: sfixed := sfixed(16 downto -12) -- [-8
);

port (
clk : in std_ulogic;
clk_en : in std_ulogic;
reset : in std_ulogic;
input : in sfixed(16 downto -14); -- [-2 2)
output : out sfixed(16 downto -14) -- [-2 2)
);

end entity df1tsos;


architecture rtl of df1tsos is

subtype numerator_type is sfixed range numerator'high downto
numerator'low;

begin


end architecture rtl;

 
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Tricky
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      07-08-2010
On 8 July, 13:27, Paul <(E-Mail Removed)> wrote:
> Hi,
>
> in the example attached I did try to parametrize my fir filter (direct
> form I second order structure) internal signals. Modelsim complains on
> it and I have no idea why and how to fix it. Anyway, the idea behind
> should be clear.
>
> Thanks,
> Olaf
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> library floatfixlib;
> use floatfixlib.math_utility_pkg.all; -- ieee_proposed for VHDL-93 version
> use floatfixlib.fixed_pkg.all; -- ieee_proposed for compatibility version
>
> entity df1tsos is
>
> * generic(
> * * numerator: * * * * *sfixed *:= sfixed(16 downto -14); *-- [-2 2)
> * * denominator: * * * *sfixed *:= sfixed(16 downto -14); *-- [-2 2)
> * * numerator_state: * *sfixed *:= sfixed(16 downto -12); *-- [-8
> * * denominator_state: *sfixed *:= sfixed(16 downto -12) * -- [-8
> * );
>
> * port (
> * * clk * * * : in *std_ulogic;
> * * clk_en * *: in *std_ulogic;
> * * reset * * : in *std_ulogic;
> * * input * * : in *sfixed(16 downto -14); *-- [-2 2)
> * * output * *: out sfixed(16 downto -14) * -- [-2 2)
> * );
>
> end entity df1tsos;
>
> architecture rtl of df1tsos is
>
> * subtype numerator_type is sfixed range numerator'high downto
> numerator'low;
>
> begin
>
> end architecture rtl;


Generics are really constants. What you've done is try defined a load
of types as generics, which isnt allowed up to VHDL 2002. you would be
able to do it in VHDL 2008 (but not like you've done it), but its not
really supported by anyone in any detail yet. You'll have to change
the generics to things like:

generic (
numerator_high : integer := 16;
numerator_low : integer := -14;
....etc
 
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