Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Components with GENERICs

Reply
Thread Tools

Components with GENERICs

 
 
Analog_Guy
Guest
Posts: n/a
 
      07-01-2010
I am interested in writing a VHDL testbench for a VHDL component with
several generics. How do I go about changing the generics during the
course of a simulation?

It is my understanding that the generic values are fixed per a given
compile of the code. I can easily manipulate ports during a
simulation, but not generics.

Can this be done through a configuration, whereby I generate a number
of configurations for each set of generic values I wish to simulate?
I would then compile the configurations, and run each separately in
ModelSim. Is there an easier way to do this on the fly with only one
simulation file?
 
Reply With Quote
 
 
 
 
Jonathan Bromley
Guest
Posts: n/a
 
      07-01-2010
On Jul 1, 8:11*am, Analog_Guy <(E-Mail Removed)> wrote:
> I am interested in writing a VHDL testbench for a VHDL component with
> several generics. *How do I go about changing the generics during the
> course of a simulation?


You can't. Generics are constants, established at elaboration
time. They are fixed for the life of the sim. Not surprising
given that you can use a generic to control things like the
width of a data bus or the number of instances of a component -
it's hard to imagine changing those things at runtime!

> Can this be done through a configuration, whereby I generate a number
> of configurations for each set of generic values I wish to simulate?


Absolutely. However, the syntax is ugly and Not Memorable,
and many people steer clear of them.

> Is there an easier way to do this on the fly with only one
> simulation file?


Modelsim (and, I'm pretty sure, other simulators too) allow you
to set generics from the command line that loads the simulation.
This provides a convenient short-cut to avoid writing a
configuration or top-level wrapper. Look up the -g and -G
options to the vsim command. I'm afraid I can't help you
with any of the other simulators, which I tend to use only
for Verilog.
--
Jonathan Bromley
 
Reply With Quote
 
 
 
 
Andy Rushton
Guest
Posts: n/a
 
      07-01-2010
Analog_Guy wrote:
> I am interested in writing a VHDL testbench for a VHDL component with
> several generics. How do I go about changing the generics during the
> course of a simulation?
>
> It is my understanding that the generic values are fixed per a given
> compile of the code. I can easily manipulate ports during a
> simulation, but not generics.
>
> Can this be done through a configuration, whereby I generate a number
> of configurations for each set of generic values I wish to simulate?
> I would then compile the configurations, and run each separately in
> ModelSim. Is there an easier way to do this on the fly with only one
> simulation file?


Yes, remember that VHDL is a concurrent language. So why not create
multiple instances in one test bench, each with different generic
values? You could wrap them in a for-generate too to generate all
permutations of the generic if that suits what you are trying to do.

I do this sometimes to do comparisons between different word-lengths to
see how it affects result accuracy. By simulating different sizes side
by side I can plot the output difference as a waveform in ModelSim.

Andy
 
Reply With Quote
 
Analog_Guy
Guest
Posts: n/a
 
      07-02-2010
On Jul 1, 8:37*am, Andy Rushton <(E-Mail Removed)> wrote:
> Analog_Guy wrote:
> > I am interested in writing a VHDL testbench for a VHDL component with
> > several generics. *How do I go about changing the generics during the
> > course of a simulation?

>
> > It is my understanding that the generic values are fixed per a given
> > compile of the code. *I can easily manipulate ports during a
> > simulation, but not generics.

>
> > Can this be done through a configuration, whereby I generate a number
> > of configurations for each set of generic values I wish to simulate?
> > I would then compile the configurations, and run each separately in
> > ModelSim. *Is there an easier way to do this on the fly with only one
> > simulation file?

>
> Yes, remember that VHDL is a concurrent language. So why not create
> multiple instances in one test bench, each with different generic
> values? You could wrap them in a for-generate too to generate all
> permutations of the generic if that suits what you are trying to do.
>
> I do this sometimes to do comparisons between different word-lengths to
> see how it affects result accuracy. By simulating different sizes side
> by side I can plot the output difference as a waveform in ModelSim.
>
> Andy


Thanks to both of you for your great suggestions. I never thought of
those
approaches! Thanks again for your help ... much appreciated.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Generics in VHDL - number of components pbartosz VHDL 2 03-09-2011 02:47 PM
generics depending on generics Soul VHDL 0 02-02-2009 09:14 AM
Can't convert a generics list of objects into a generics list ofinterfaces Juergen Berchtel Java 1 05-20-2005 02:07 PM
Can Choice components respond to keyboard input like HTML Choice components? Mickey Segal Java 0 02-02-2004 10:59 PM
Re: Multi-dimentional arrays in components using generics Willem Oosthuizen VHDL 1 07-09-2003 12:13 PM



Advertisments