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VHDL connecting block different timing

 
 
niyander
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      06-25-2010
hello,

i have created two vhdl designs, a floating point adder and a binary
to floating point conversion unit. I wish to connect both the designs,
but when i simulate both the design in modelsim, floating point adder
takes 8ns and binary to floating point conversion unit takes 6ns to
process completely, now if i connect both of them together (input
flows first into binary to floating point unit and after it to the
adder unit), now my question is if i connect them will they be working
properly without any timing issue for many inputs one after another
and not skip any input? and if not then how can i connect them to work
synchronously. I would really appreciate if some one can help me.

I have consulted this with one of my friend and he suggested me to use
latch/register design, can any one point me to an example of
connecting blocks using latch/register method in vhdl.

thanks
niyander
 
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KJ
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      06-25-2010
On Jun 25, 11:02*am, niyander <(E-Mail Removed)> wrote:
> now my question is if i connect them will they be working
> properly without any timing issue for many inputs one after another
> and not skip any input?


- For function verification, I would suggest writing a simulation
testbench to test that your design is working properly.

- For timing verification, I would suggest that you specify the input
setup time, clock
to output delay, propogation delay and clock cycle requirements to
your synthesis tool and then verify that the static timing analysis
report that gets generated shows no errors.

You haven't provide any useful information for anybody in this group
to give you even a weak 'yes' or 'no' answer to your question. It's
your design after all.

> and if not then how can i connect them to work
> synchronously. I would really appreciate if some one can help me.
>


I would look for some good VHDL textbooks.

> I have consulted this with one of my friend and he suggested me to use
> latch/register design, can any one point me to an example of
> connecting blocks using latch/register method in vhdl.
>


As well as some digital design textbooks.

KJ
 
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