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synthesis of exit in for loop

ikbangesh ikbangesh is offline
Junior Member
Join Date: May 2010
Posts: 2
Hi friends
I am new to FPGA world. I have one question, can exit command in for loop be synthesized ? if exit is true how many logic copies of for loop will be created.

for i in 0 to 6 loop
if i =4 then
end if;
end loop;

Many thanks
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eliascm eliascm is offline
Join Date: Jan 2009
Posts: 42
The loop you have presented will not synthesize any hardware. If this is part of some process that you want to synthesize you need to post the entire code before someone can help you.
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