Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > D flip flop setup and hold timings.

Thread Tools

D flip flop setup and hold timings.

luvdhams23 luvdhams23 is offline
Junior Member
Join Date: Jun 2010
Posts: 1
Hello everyone,
I am new to this Website and as well as VHDL??

i have got exams soon and need to work out few problems in vhdl, hope you guys help me quickly...

problem 1)

how do i make vhdl code for asynchronous reset D flip flop by including setup (SUT) and hold (HT) violations ? ? ? ?

Please help me guys on this..appreciated !!
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
IC area of flip-flop and SRAM? Weng Tianxiang VHDL 1 05-23-2004 04:05 PM
No difference between .. and ... flip/flop operators? Phil Tomson Ruby 37 02-08-2004 02:18 AM
4 bit divisor with flip-flop ? eric VHDL 15 02-05-2004 03:31 AM
flip flop operator and assignment Phil Tomson Ruby 15 02-04-2004 09:25 PM
Flip Flop Synchronization John VHDL 3 01-05-2004 05:58 PM