Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Re: Signal/Variable Initial Vaues and Evils of Asynchronous Reset

Thread Tools

Re: Signal/Variable Initial Vaues and Evils of Asynchronous Reset

Posts: n/a
On May 29, 9:56*pm, Wendigo <(E-Mail Removed)> wrote:
> I have a book that says the following regarding initial values for signals
> and variables...
> "VARIABLE control: BIT := 0;
> ...Also, like in the case of a SIGNAL, the initial value in the syntax above
> is not synthesizable, being only considered in simulations."
> The documentation from my vendor explicitly states that it supports this
> (for signals and variables that are registered at least):
> "When you give a register an initial value in a declaration, XST sets this
> value on the output of the register at global reset, or at power up. The
> assigned value is carried in the NGC file as an INIT attribute on the
> register, and is independent of any local reset."
> Are there certain vendors that don't support this? *Is it not
> supported by certain technologies? *(ASICs, perhaps?) *
> I'm just curious how portable (across tools and technologies) this is.
> Also... *This isn't necessarily VHDL related but I've read some of the
> messages in this group about the problems with asynchronous reset and now
> I have a question.
> Can the GSR signal (Global Set/Reset, I'm guessing this is a
> vendor-specific term) be used for synchronous reset? *I don't see anything
> in the datasheet for my particular device (Xilinx XC9572XL) that says
> that it can or can't. *My design runs at only 32.768kHz so I'm worried the
> GSR signal won't still be asserted when a rising clock edge comes along.
> I couldn't find any app. notes that specifically state that GSR will be
> asserted for a least one complete clock cycle in order to guarantee a
> synchronous reset.

Altera wont infer power up values using default assignments for
registers, but they are obviously very useful in simulation. It will
however allow you to set the power-up values of an infered ram either
via a constant or function call (though they still wont allow you to
use textio to read a text file like Xilinx do!) Altera will infer
power up reset values from the asynchronous reset functionality
though, so it can be useful to to create an async reset even if you
plan to connect it to '0';
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Re: Signal/Variable Initial Vaues and Evils of Asynchronous Reset Tricky VHDL 0 05-29-2010 11:30 PM
Re: Signal/Variable Initial Vaues and Evils of Asynchronous Reset Mike Treseler VHDL 0 05-29-2010 10:21 PM
Evils of M$ and C++ability Malcolm McLean C Programming 19 04-10-2007 10:32 AM
[ANN] AP4R, Asynchronous Processing for Ruby, initial release Ruby 4 09-04-2006 02:27 AM
DVD Verdict reviews: HOLLOW MAN 2, SPLIT SECOND, EVILS OF THE NIGHT, and more! DVD Verdict DVD Video 0 05-19-2006 08:27 AM