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[jmcoreymv]

I'm trying to figure out if there's a way to write VHDL code that can initialize a ROM targeting a block ram inside a Xilinx Spartan 3/6 series FPGA. Synthesis would be done through Synplify Pro. According to the Synplify manual, it seems ROM inference with initialization only works for the Virtex FPGAs? Right now I'm using coregen but it has become very tedious since I have about 10 cores I need to generate from .COE files.