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divider ip core problem!

charko charko is offline
Junior Member
Join Date: Apr 2010
Posts: 10
Hi everybody!
I want to implement in vhdl a divider. So i want to use an ip core if i want to have a fast divider.
The divider can used for the calcul of interpolator. The algorithm for interpolator linear is : f= ya + lamda x ( yb -ya) and lamda= (x-xa)/(x-xb).
When i write a code vhdl ( vhdl structural) for adder, multiplier and substractor i compile it and i simulate it and evrything is ok.
So When i implement an ip core divider and simulate it i have at divider output
You can show in the attachement , the picture for the architecture, picture divider simulation and picture of the interpolation simulation.

I hope that i clarify my problem.
I will be grateful for your help.
Thank you.

PS: Sorry for my bad english.
Attached Images
File Type: jpg divider simulation.jpg (172.1 KB, 4 views)
File Type: jpg interpolator architecture.jpg (152.5 KB, 2 views)
File Type: jpg interpolator simulation.jpg (211.2 KB, 2 views)
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