Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > divider ip core problem!

Reply
Thread Tools

divider ip core problem!

 
 
charko charko is offline
Junior Member
Join Date: Apr 2010
Posts: 10
 
      05-27-2010
Hi everybody!
I want to implement in vhdl a divider. So i want to use an ip core if i want to have a fast divider.
The divider can used for the calcul of interpolator. The algorithm for interpolator linear is : f= ya + lamda x ( yb -ya) and lamda= (x-xa)/(x-xb).
When i write a code vhdl ( vhdl structural) for adder, multiplier and substractor i compile it and i simulate it and evrything is ok.
So When i implement an ip core divider and simulate it i have at divider output
zero.
You can show in the attachement , the picture for the architecture, picture divider simulation and picture of the interpolation simulation.

I hope that i clarify my problem.
I will be grateful for your help.
Thank you.
Charko

PS: Sorry for my bad english.
Attached Images
File Type: jpg divider simulation.jpg (172.1 KB, 4 views)
File Type: jpg interpolator architecture.jpg (152.5 KB, 2 views)
File Type: jpg interpolator simulation.jpg (211.2 KB, 2 views)
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
MCU clock divider vs. VHDL divider Matt Clement VHDL 3 04-28-2006 01:24 PM
Core Solo & Core Duo are not Core microarchitecture; 65nm Pentium M chips bigal Hardware 0 03-22-2006 11:24 AM
Frequency divider Patrick VHDL 6 05-21-2004 05:32 AM
clk divider Schmigz VHDL 7 04-15-2004 08:23 AM
SOS : 4-bit binary divider circuit PLEASE!!!!!!! kpk VHDL 37 01-06-2004 02:53 PM



Advertisments