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Type of actual ports is not compatible with type of ports of entity.

mreister mreister is offline
Junior Member
Join Date: Aug 2008
Posts: 10
I have a realy anoying error on my hands. I think I understand what its trying to tell me but, I cant seem to find the mismatch. As I understand it the error, which apears in the title of this post, is telling my that the actual signal that I am assigning to the entity of uart_tx is a diffrent type than the actual port declaration. If this is so I should be able to find where I am assigning the wrong data type and that should be that. But here is the relavent code:
Top module:
entity uart is
-- Default setting:
-- 19200 baud, 8 data bits, 1 stop bit, 2^2 FIFO
DBIT: integer := 8; -- # data bits
SB_TICK: integer :=16; -- # ticks for stop bits , 16/24/32
-- # for 1/1.5/2 stop bits
DVSR: integer := 163; -- # baud rate divisor
-- # DVSR = 50M/(16*baud rate)
DVSR_BIT: integer := 8; -- # bits of DVSR
FIFO_W: integer := 2 -- # addr bits of FIFO
-- # words in FIFO=2^FIFO_W
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
rd_uart : in STD_LOGIC;
wr_uart : in STD_LOGIC;
rx : in STD_LOGIC;
w_data : in STD_LOGIC_VECTOR (7 downto 0);
tx_full : out STD_LOGIC;
rx_empty : out STD_LOGIC;
r_data : out STD_LOGIC_VECTOR (7 downto 0);
tx : out STD_LOGIC);
end uart;

architecture str_arch of uart is
signal tick: STD_LOGIC;
signal rx_done_tick: STD_LOGIC;
signal tx_fifo_out: STD_LOGIC_VECTOR(7 downto 0);
signal rx_data_out: STD_LOGIC_VECTOR(7 downto 0);
signal tx_empty, tx_fifo_not_empty: STD_LOGIC;
signal tx_done_tick: STD_LOGIC;

uart_tx_unit: entity work.uart_tx(arch)
generic map(DBIT=>DBIT,SB_TICK=>SB_TICK)
port map(clk=clk,
tx_done_tick=> tx_done_tick,
tx=> tx);
end str_arch;

-- the entity in question

entity uart_tx is
DBIT: integer := 8;
SB_TICK: integer := 16
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
tx_start : in STD_LOGIC;
s_tick : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (7 downto 0);
tx_done_tick : out STD_LOGIC;
tx : out STD_LOGIC);
end uart_tx;

architecture arch of uart_tx is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type;
signal s_reg, s_next: unsigned(3 downto 0);
signal n_reg, n_next: unsigned(2 downto 0);
signal b_reg, b_next: std_logic_vector(7 downto 0);
signal tx_reg, tx_next: std_logic;
end arch;

---- I didn't include the behavior of the uart_tx because i didn't think it was relivent to the question. I checked for a type mismatch a bunch of times but I cant find it.... Any suggestions?
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mreister mreister is offline
Junior Member
Join Date: Aug 2008
Posts: 10
I forgot the include a '>' in one of the portmap declaration..... didn't seem to be a very accurate error message
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