On Mon, 17 May 2010 09:13:35 -0700 (PDT), Andy wrote:
>Unfortunately, declarations within a generate statement are local to
>the generate's block, and furthermore, generate statements cannot be
>located in the declarative region. This is one glaring limitation to
>the generate capability: conditional declarations useable outside the
>generate statement.
right, although of course you can see the reasoning
behind that.
>You could use a function for the declaration initializer of
>internal_val...? Similarly to what the OP was doing with unconstrained
>ports, declare internal_val as unconstrained SLV, with a function call
>to define an initial value
That's fine for constants, but surely not for a signal
or variable?
> I don't think you could replace the generate statements with
>the initializer function, since the generate statements created the
>correct concurrent assignment also.
I still think it's OK: the declaration of internal_val would
be outside any generate, determined by the properties
of other ports etc (not forgetting that functions can be
used to determine the values of constants that control
a signal's declaration). And then a generate could
conditionally create a process, in whose declarative
region there is a function used to build the signal's
value so that process can duly drive it.
I agree, though, that it's all a bit of a faff. Probably a
few generics on the entity would make for a neater job.
Have pity on me. As I complained earlier, I'm currently
in Verilog land, where such things are not permitted to
appear even in nocturnal fantasies.
--
Jonathan Bromley
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