Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Default value for an unconstrained port

Reply
Thread Tools

Default value for an unconstrained port

 
 
Jonathan Bromley
Guest
Posts: n/a
 
      05-17-2010
On Mon, 17 May 2010 09:13:35 -0700 (PDT), Andy wrote:

>Unfortunately, declarations within a generate statement are local to
>the generate's block, and furthermore, generate statements cannot be
>located in the declarative region. This is one glaring limitation to
>the generate capability: conditional declarations useable outside the
>generate statement.


right, although of course you can see the reasoning
behind that.

>You could use a function for the declaration initializer of
>internal_val...? Similarly to what the OP was doing with unconstrained
>ports, declare internal_val as unconstrained SLV, with a function call
>to define an initial value


That's fine for constants, but surely not for a signal
or variable?

> I don't think you could replace the generate statements with
>the initializer function, since the generate statements created the
>correct concurrent assignment also.


I still think it's OK: the declaration of internal_val would
be outside any generate, determined by the properties
of other ports etc (not forgetting that functions can be
used to determine the values of constants that control
a signal's declaration). And then a generate could
conditionally create a process, in whose declarative
region there is a function used to build the signal's
value so that process can duly drive it.

I agree, though, that it's all a bit of a faff. Probably a
few generics on the entity would make for a neater job.

Have pity on me. As I complained earlier, I'm currently
in Verilog land, where such things are not permitted to
appear even in nocturnal fantasies.
--
Jonathan Bromley
 
Reply With Quote
 
 
 
 
Andy
Guest
Posts: n/a
 
      05-17-2010
On May 17, 2:43*pm, Jonathan Bromley <(E-Mail Removed)>
wrote:
>
> That's fine for constants, but surely not for a signal
> or variable?
>


True, you'd have to use a function to initialize an unconstrained
constant, then you could use the constant's range to declare the
variable/signal.

You have my sympathy. Somehow I think verilog must be more kind to
those who've never known the benefits of VHDL. Otherwise, who would
prefer it? But that's a different thread...

Andy
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
How to make Unconstrained std_logic_vector port :) mido_nour1 VHDL 2 07-31-2009 05:55 PM
Unconstrained array of unconstrained vector. Amal VHDL 5 03-08-2006 05:02 PM
Unconstrained array for output port in generic :/ killerhertz@gmail.com VHDL 5 05-27-2005 02:18 PM
type convertion of an unconstrained output in a port map ygrugni@hotmail.com VHDL 8 02-10-2005 06:53 PM
How to specify default value to a variable of unconstrained type INSIDE a VHDL procedure ? Pankaj VHDL 2 08-23-2004 04:36 AM



Advertisments