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Im trying to do some fixed point math using the fixed point package (I
thought Id try and avoid all the ballache of using numeric_std for
once!). I get the following error from quartus:

Error (10346): VHDL error at fixed_pkg_c.vhdl(4780): formal port or
parameter "size_res" must have actual or default value
Error (10346): VHDL error at fixed_pkg_c.vhdl(4782): formal port or
parameter "size_res2" must have actual or default value
Error (10657): VHDL Subprogram error at test_build.vhd(56): failed to
elaborate call to subprogram "sfixed_high"

Over the following line in my VHDL:

subtype mult_op_t is sfixed( sfixed_high(video, '*',
coeffs( coeffs'low(1), coeffs'low(2) ) )
downto
sfixed_low( video, '*',
coeffs( coeffs'low(1), coeffs'low(2) ) )
);

Am I missing something, or am I confusing quartus with all my existing
subtypes?

Heres all the type declarations and the signals used:

subtype filter_word_t is sfixed(11 downto -4);
subtype coeff_t is sfixed(1 downto -16);
type coeff_array_t is array(integer range <>, integer range <>) of
coeff_t;

In entity:
video : in filter_word_t;
coeffs : in coeff_array_t(0 to 2, 0 to 2)

Can you do something like (I haven't actually tried it, so "hold my
beer and watch this"):

constant a,b : coeff_t := (others => '0');
constant axb : sfixed := a * b;
subtype mult_op_t is sfixed(axb'range);

Andy

Tricky wrote:
> Im trying to do some fixed point math using the fixed point package (I
> thought Id try and avoid all the ballache of using numeric_std for
> once!). I get the following error from quartus:
>
> Error (10346): VHDL error at fixed_pkg_c.vhdl(4780): formal port or
> parameter "size_res" must have actual or default value
> Error (10346): VHDL error at fixed_pkg_c.vhdl(4782): formal port or
> parameter "size_res2" must have actual or default value
> Error (10657): VHDL Subprogram error at test_build.vhd(56): failed to
> elaborate call to subprogram "sfixed_high"
>
> Over the following line in my VHDL:
>
> subtype mult_op_t is sfixed( sfixed_high(video, '*',
> coeffs( coeffs'low(1), coeffs'low(2) ) )
> downto
> sfixed_low( video, '*',
> coeffs( coeffs'low(1), coeffs'low(2) ) )
> );
>
> Am I missing something, or am I confusing quartus with all my existing
> subtypes?

I suspect that Quartus cannot synthesise sfixed_high and sfixed_low as
constant expressions, which it needs to do to calculate the bounds of
mult_op_t. Try substituting literal values to see if that fixes it. If
it does, inline the size calculation so as to exclude these functions
(i.e. using literals, attribute values, * and + operators only) and see
if it still works.

>
> Heres all the type declarations and the signals used:
>
> subtype filter_word_t is sfixed(11 downto -4);
> subtype coeff_t is sfixed(1 downto -16);
> type coeff_array_t is array(integer range <>, integer range <>) of
> coeff_t;
>
> In entity:
> video : in filter_word_t;
> coeffs : in coeff_array_t(0 to 2, 0 to 2)
>

On 24 Apr, 17:58, David Bishop <dbis...@vhdl.org> wrote:
> Tricky wrote:
> > Im trying to do some fixed point math using the fixed point package (I
> > thought Id try and avoid all the ballache of using numeric_std for
> > once!). I get the following error from quartus:
>
> First, get the version specifically designed for Quartus.
> You will find it athttp://www.vhdl.org/fphdl
>
>
>
> > Error (10346): VHDL error at fixed_pkg_c.vhdl(4780): formal port or
> > parameter "size_res" must have actual or default value
> > Error (10346): VHDL error at fixed_pkg_c.vhdl(4782): formal port or
> > parameter "size_res2" must have actual or default value
> > Error (10657): VHDL Subprogram error at test_build.vhd(56): *failed to
> > elaborate call to subprogram "sfixed_high"
>
> > Over the following line in my VHDL:
>
> > subtype mult_op_t is sfixed( sfixed_high(video, '*',
> > coeffs( coeffs'low(1), coeffs'low(2) ) )
> > * * * * * * * * * * * * * * * * * downto
> > * * * * * * * * * * * * * * * *sfixed_low( video, '*',
> > coeffs( coeffs'low(1), coeffs'low(2) ) )
> > * * * * * * * * * * * * * * *);
>
> > Am I missing something, or am I confusing quartus with all my existing
> > subtypes?
>
> It doesn't like the fact that "video" is an input, and thus can have a
> variable length depending on generics. * This is an Quartus "gotcha"
> because of the way their third party VHDL compiler works.
>
> > Heres all the type declarations and the signals used:
>
> > subtype filter_word_t is sfixed(11 downto -4);
> > subtype coeff_t * * * is sfixed(1 *downto -16);
> > type coeff_array_t is array(integer range <>, integer range <>) of
> > coeff_t;
>
> > In entity:
> > video * * * * * * * * * * : in *filter_word_t;
> > coeffs * * * * * * * * * *: in *coeff_array_t(0 to 2, 0 to 2)
>
> I would do this as:
> subtype mult_op_t is sfixed (video'high+coeff_t'high+1
> * * * * * * * * * * * * * * * downto video'low + coeff_t'low);
>
> Please tell me if this fixes your problem. * I wrote this package and
> I'm collecting these things.

Thanks David - that fix made it pass the syntax checker.
Now I just have to tell altera that arrays of arrays constitute
multiple memories, not a million registers and a decoder.