Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > warning when synthesizing

Reply
Thread Tools

warning when synthesizing

 
 
TheRekz TheRekz is offline
Junior Member
Join Date: Apr 2010
Posts: 1
 
      04-21-2010
When I synthesize the code below it gives me the warning:

One or more signals are missing in the sensitivity list of always block

I know this is because I don't have mul inside the sensitivity list and I don't want it to be... so what should I do? Is there a way to get rid off mul completely?

Code:
input signed[31:0] Reg1;
input signed[31:0] Reg2;
input[4:0] Control;
output[31:0] Result;
output Zero, Sign;

reg signed[31:0] Result;
reg[63:0] mul;
reg Zero, Sign;


always @(Reg1, Reg2, Control) begin
case (Control)
  5'b00001: // ADD
	   Result =Reg1+Reg2;
  5'b00010: // SUBTRACT
	   Result =Reg1-Reg2; 
  5'b00100: // AND
		Result=Reg1&Reg2;
  5'b01111: // MUL
	   begin
			mul = Reg1 * Reg2;
			Result = mul[31:0];
		end
  default:
		Result = Reg1;
endcase
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
How is Synopsys DC 2004.06-SP2's capability in synthesizing large designs. Novice VHDL 5 03-18-2006 08:32 AM
Synthesizing high-density designs in Quartus Divyang M VHDL 4 08-08-2005 08:20 PM
Problem in synthesizing function sps VHDL 1 08-06-2005 06:56 AM
Avoiding "Bad Synchronous Description" Error when Synthesizing Takuon Soho VHDL 5 03-09-2005 05:41 AM
Synthesizing a design with RAM. Kelvin @ Singapore VHDL 0 09-08-2003 11:37 PM



Advertisments