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display the value of a std_ulogic with attributes (or something likethat)

 
 
whygee
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      04-15-2010
Hi !

my today's challenge is to write (report) the value
of a std_ulogic with the least code bloat.
So I want to make a string out of a std_ulogic.

I have seen a conversion function in the synopsys package
but I want to avoid it. It works by defining an array type,
then a constant of this type, and finally the conversion
is a lookup in this constant table.

However this constant table should not have been re-defined,
it is already provided by the package std_logic_1164 :

TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);

however the resulting structure is not an array but a type :-/
I have searched several combinations of attributes but I don't
succeed in getting a character out of this


any hint ?
I just want to display one signal ...
yg
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whygee
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      04-15-2010
Alan Fitch wrote:
> Now is this bloated code...
>
> report std_ulogic'image(mysig);


damnit, that's even simpler than I thought !

> -- image valid in vhdl 93 onwards - doesn't work composite types (arrays
> and records)

well that's not an issue.

oh, and I also tried to avoid giving the signal's name
as a parameter to my "observe" procedure, like in

report mysig'simple_name & "=" & std_ulogic'image(mysig);

however, it displays "mysig" all the time,
not the name of the signal that is given as a parameter...
Well, I reverted to giving an additional string parameter.
There, I have less hopes of simplicity...

So now I'm going forward in my exploration of the simulator's guts.

> regards

thanks again !
> Alan

yg
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whygee
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      04-15-2010
Alan Fitch wrote:
> On 15/04/2010 15:35, whygee wrote:
>> report mysig'simple_name & "=" & std_ulogic'image(mysig);
>>
>> however, it displays "mysig" all the time,
>> not the name of the signal that is given as a parameter...
>> Well, I reverted to giving an additional string parameter.
>> There, I have less hopes of simplicity...

>
> Yes, that's a "feature". I wrote some coverage procedures to dump values
> to a file, and had to do the same thing (pass the attribute of the
> actual parameter to the procedure instead of using the attribute of the
> formal parameter). I was using 'INSTANCE_NAME to get the full path, but
> the principle's the same.

yup, I found that attribute too in some docs...

>> So now I'm going forward in my exploration of the simulator's guts.

> Good luck...

thanks
well, I succeeded in doing a working proof of concept,
and now I have to document every corner of the code,
which takes most of the time.
But it's the job I have chosen so I won't complain

thank you again for all your insight,

> Alan

yg
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Jonathan Bromley
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      04-15-2010
On Apr 15, 2:44*pm, Alan Fitch <(E-Mail Removed)> wrote:

> Now is this bloated code...
> report std_ulogic'image(mysig);


Certainly not bloated, but (as Alan very well knows) it may produce
more bloated output than you bargained for... given an enumeration
literal that's a character, like '0' in std_ulogic, 'image will
return a THREE-CHARACTER string including both the single quotes!
So you may prefer this, if you're using the result for any other
purpose than a simple single-bit display:

function to_character(u: std_ulogic) return character is
constant s: string(1 to 3) := std_ulogic'image(u);
begin
return s(2);
end;

Off-topic: I was introduced a few days ago to the coinage
"enumeral", meaning "enumeration literal". I don't know
how long it's been around, but it's quite cute!
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whygee
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      04-16-2010
Jonathan Bromley wrote:
> it may produce
> more bloated output than you bargained for... given an enumeration
> literal that's a character, like '0' in std_ulogic, 'image will
> return a THREE-CHARACTER string including both the single quotes!

With GHDL this behaviour does not appear.
So I simply wrote a package with (among others) :

procedure observe_std_ulogic
(name: string; s:std_ulogic) is
begin
report name & "=" & std_ulogic'image(s);
end procedure;

That's all I wanted to have, it outputs the signal names,
values and times. In one architecture where there is a clk signal,
I just write directly :

architecture xyz of abcd is
signal clk: std_ulogic;
begin
observe_std_ulogic("clk",clk);

-- drive clk here
end xyz;

There is no explicit process so
when the number of observed signals increases,
this little procedure pays the initial efforts

> So you may prefer this, if you're using the result for any other
> purpose than a simple single-bit display:
>
> function to_character(u: std_ulogic) return character is
> constant s: string(1 to 3) := std_ulogic'image(u);
> begin
> return s(2);
> end;


which tool(s) require(s) this trick ?

> Off-topic: I was introduced a few days ago to the coinage
> "enumeral", meaning "enumeration literal". I don't know
> how long it's been around, but it's quite cute!

I learn everyday too
And I remain amazed by the sophistication of VHDL.
I wish VHDL'2008 gets implemented in GHDL soon

> Jonathan Bromley

yg
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Jonathan Bromley
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      04-16-2010
On Apr 16, 2:21*am, whygee <(E-Mail Removed)> wrote:
> Jonathan Bromley wrote:
> > given an enumeration
> > literal that's a character, like '0' in std_ulogic, 'image will
> > return a THREE-CHARACTER string including both the single quotes!

>
> With GHDL this behaviour does not appear.


GHDL is definitely wrong about this.

The problem is that VHDL enumerals (!) can be either identifiers,
or characters. And you can mix them in a given type. So consider
this (pathological) type:

type foutu is ('a', a, 'b', b);

Now, what should I get from this code?

for i in foutu loop
report "value is <" & foutu'image(i) & ">";
end loop;

The correct answer, of course, is:
value is <'a'>
value is <a>
value is <'b'>
value is <b>

But it seems that GHDL would produce ambiguous results,
with <a> appearing twice. Not good.
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whygee
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      04-16-2010
Hi !

(sorry, I sent it directly to Jonathan)

Jonathan Bromley wrote:
> GHDL is definitely wrong about this.

that's big claim,
does it mean that my favorite SW is badly behaving?
I had to test


entity test_type is
end test_type;

architecture test of test_type is
type foutu is ('a', a, 'b', b);
begin
process
begin
for i in foutu loop
report "value is <" & foutu'image(i) & ">";
end loop;
wait;
end process;
end test;

$ ghdl -a test_type.vhdl
$ ghdl -e test_type
$ ./test_type
test_type.vhdl:17:7:@0msreport note): value is <'a'>
test_type.vhdl:17:7:@0msreport note): value is <a>
test_type.vhdl:17:7:@0msreport note): value is <'b'>
test_type.vhdl:17:7:@0msreport note): value is <b>

OK I feel better now

> The problem is that VHDL enumerals (!) can be either identifiers,
> or characters. And you can mix them in a given type. So consider
> this (pathological) type:
> type foutu is ('a', a, 'b', b);

I didn't even know it was possible

> But it seems that GHDL would produce ambiguous results,
> with <a> appearing twice. Not good.

I note the "would".
when in doubt, it's a good idea to test, it took only 2 minutes.

And I learnt something crazy today again

~~~~~

BTW, it seeems that this discussion was triggered by one
of my messages :

> With GHDL this behaviour does not appear.
> So I simply wrote a package with (among others) :
>
> procedure observe_std_ulogic
> (name: string; s:std_ulogic) is
> begin
> report name & "=" & std_ulogic'image(s);
> end procedure;
>
> That's all I wanted to have, it outputs the signal names,
> values and times.


I was wrong in the first place : when I run my code, I see

rt_clk.vhdl:30:5:@0msreport note): clk='0'

the "'" are here, I just did not notice, or cared.
Sorry for all this excitement.


Best regards,
> Jonatban Bromley

s/b/h/ ?
yg
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whygee
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      04-16-2010
Alan Fitch wrote:
> Have a look at the CHARACTER data type in std.standard.

I see it from time to time, it appears here and there
in tutorials, books etc. and I also look at the std and ieee files
to solve some issues.

> I sometimes amuse my trainees on Expert VHDL by demonstrating printing
> the BEL (CTRL-G) character to standard output.
> Or why not try
> report "hmm, more than one " & CR & LF & "line";
> Those crazy engineers...

yes, if it can be done, why not do it ?
the "crazy" part is to imagine it...

yes, VHDL is crazy too

> Alan

yg
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Jonathan Bromley
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      04-17-2010
On Apr 16, 12:32*pm, whygee <(E-Mail Removed)> wrote:

> Jonathan Bromley wrote:
> > GHDL is definitely wrong about this.

>
> that's big claim,
> does it mean that my favorite SW is badly behaving?


Apologies for the lack of precision - I don't use GHDL, so
I should have said "the behaviour you reported is wrong".
Nice to know that GHDL is innocent here.
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whygee
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      04-17-2010
Jonathan Bromley wrote:
> On Apr 16, 12:32 pm, whygee <(E-Mail Removed)> wrote:
>> Jonathan Bromley wrote:
>>> GHDL is definitely wrong about this.

>> that's big claim,
>> does it mean that my favorite SW is badly behaving?

>
> Apologies for the lack of precision - I don't use GHDL, so
> I should have said "the behaviour you reported is wrong".
> Nice to know that GHDL is innocent here.

that's Usenet

have a nice week-end,

> Jonathan Bromley

yg

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