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cannot be synthesized

 
 
uche
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      04-03-2010
Hi,

I am trying to find out why my following code cannot synthesize.
Please give me suggestions on how to fix it.

input_counter: process(rst, clk)
begin
if(rst'event and rst = '1') then
CNT <= 0;
OFFSET <= "00000000000000000000000000000000";
buffer_int(31 downto 0) <= "00000000000000000000000000000000";
buffer_int2(31 downto 0) <= "00000000000000000000000000000000";
xn_re(31 downto 0)<= "00000000000000000000000000000000";
elsif (clk'event and clk = '1') then
--the following lines are exectued at the same time, when count is 1
offset it 0 !
CNT <= CNT + 1;
OFFSET <= CONV_STD_LOGIC_VECTOR(CNT, 32);
buffer_int(31 downto 0) <= buffer_int(31 downto 0);
buffer_int2(31 downto 0) <= buffer_int2(31 downto 0);
xn_re(31 downto 0)<= xn_re(31 downto 0);
elsif(rfd = '1' ) then
buffer_int(31 downto 0) <= dout(31 downto 0);
buffer_int2(31 downto 0) <= buffer_int(31 downto 0);
xn_re(31 downto 0)<= buffer_int2(31 downto 0);

end if;
end process;

Thanks,
 
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jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      04-03-2010
Code:
input_counter: process(rst, clk)
begin
    if(rst = '1') then
         CNT <= 0;
         OFFSET <= "00000000000000000000000000000000";
          buffer_int(31 downto 0) <= "00000000000000000000000000000000";
          buffer_int2(31 downto 0) <= "00000000000000000000000000000000";
          xn_re(31 downto 0)<= "00000000000000000000000000000000";
      elsif (clk'event and clk = '1') then
              if rfd = '1'  then
                   buffer_int(31 downto 0) <= dout(31 downto 0);
                   buffer_int2(31 downto 0) <= buffer_int(31 downto 0);
                   xn_re(31 downto 0)<= buffer_int2(31 downto 0);
              else
          --the following lines are exectued at the same time, when count is 1 offset it 0 !
                CNT <= CNT + 1;
                OFFSET <= CONV_STD_LOGIC_VECTOR(CNT, 32);
                 buffer_int(31 downto 0) <= buffer_int(31 downto 0);
                 buffer_int2(31 downto 0) <= buffer_int2(31 downto 0);
                 xn_re(31 downto 0)<= xn_re(31 downto 0);
            end if;
     end if;
end process;

This should solve your problem - your welcome
 
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KJ
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Posts: n/a
 
      04-03-2010
On Apr 3, 3:50*am, uche <(E-Mail Removed)> wrote:
<snip>

In general, you'll do better posting just what the error was, but in
this case it is most likely because your process is looking for edges
on rst or clk

if(rst'event and rst = '1') then
...
elsif (clk'event and clk = '1') then

You probably mean this to be something that gets asynchronously reset
which would be...

if(rst = '1') then
...
elsif (clk'event and clk = '1') then

Or perhaps you mean to have a synchronous reset which would be...

if (clk'event and clk = '1') then
if(rst = '1') then
...
else
...

Kevin Jennings
 
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Philippe
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      04-05-2010
On Apr 3, 9:50 am, uche <(E-Mail Removed)> wrote:
> begin
> if(rst'event and rst = '1') then


> elsif (clk'event and clk = '1') then


> elsif(rfd = '1' ) then


> end if;


Trying to guess which behavior you want to implement, I think you
might want something like this:

if(rfd = '1' ) then -- asyncronous reset RFD
....
elsif (clk'event and clk = '1') then
if(rst = '1') then -- synchronous reset RST
...
else
...
end if;
end if;

Also, you can change the way you write bit string literals. These
three statements all mean the same thing:
OFFSET <= "00000000000000000000000000000000";
OFFSET <= X"00000000";
OFFSET <= (other => '0');

Philippe

--
Philippe Faes
http://www.sigasi.com


 
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Andy
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Posts: n/a
 
      04-06-2010
The if/else rfid = '1' action cannot be a reset, since it assigns
dynamic values to the registers in the OP's code. The structure of
these assignments appears to be a synchronous condition (shift
register), which should not be an else to the clock/reset if-tree, but
should be an "if rfid = '1' then" statement subordinate to "if
clk'event and clk = '1' then";

To the OP:

Do not use CONV_STD_LOGIC_VECTOR(). It comes from the non-ieee-
standard packages originated by Synopsys, but not equally supported by
others. Use ieee.numeric_std instead. It declares types signed and
unsigned, is officially approved by IEEE, and is supported by all
vendors.

Use "if rising_edge(clk) then" instead of "if clk'event and clk = '1'
then". The former is more descriptive and safer if metavalues are
encountered on the clock signal in simulation.

In general, the template for an asyncrhonously reset, synchronous
(clocked) process is as follows:

<label>: process (clk, rst) is
<variable declarations>
begin
if rst = '1' then
<reset assignments>
elsif rising_edge(clk) then
<synchronous assignments>
end if;
end process <label>;

Any conditionals in the <synchronous assignments> section become
multiplexers, clock enables, etc. feeding registers.

In the above template, any register not reset in the <reset
assignments> will get a clock feedback mux (disabled clock enable on
rst) to keep them from updating if rst is active, as dictated by the
behavior of the code (if rst is active, the <synchronous assignments>
do not execute).

If you need to asynchronously reset some registers, while keeping
others running, then use the following template:

<label>: process (rst, clk) is
<variable declarations>
begin
if rising_edge(clk) then
<synchronous assignments>
end if;
if rst = '1' then
<reset assignments>
end if;
end process <label>;

This template only resets those registers that are assigned in <reset
assignments> and leave any others running normally during rst.

Andy

 
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