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help with ISE+modelsim XEIII

 
 
totohaha totohaha is offline
Junior Member
Join Date: Mar 2009
Posts: 5
 
      04-01-2010
I have a System Generator design and I have build it to ""HDL Netlist", and select the "Create testbench" in Sys Gen. Then I use ISE to do the post-route simulation. Now I have following errors:

My Enviroment:

ISE 10.1.03 with service pack 3

Modelsim XEIII with pre-compiled library.


# Loading simprim.x_buf(x_buf_v)
# Loading simprim.x_obuf(x_obuf_v)
# ** Error: (vsim-3733) ./netgen/par/test_cw_timesim.vhd(1487: No default binding for component at 'gateway_out_10_obuf'.
# (Generic 'tpd_gts_o' is not on the entity.)
# Region: /test_tb/sysgen_dut/gateway_out_10_obuf
# ** Error: (vsim-3733) ./netgen/par/test_cw_timesim.vhd(14886): No default binding for component at 'gateway_out_11_obuf'.
# (Generic 'tpd_gts_o' is not on the entity.)
# Region: /test_tb/sysgen_dut/gateway_out_11_obuf
# ** Error: (vsim-3733) ./netgen/par/test_cw_timesim.vhd(14894): No default binding for component at 'gateway_out_12_obuf'.
# (Generic 'tpd_gts_o' is not on the entity.)
# Region: /test_tb/sysgen_dut/gateway_out_12_obuf
# ** Error: (vsim-3733) ./netgen/par/test_cw_timesim.vhd(14902): No default binding for component at 'gateway_out_13_obuf'.
# (Generic 'tpd_gts_o' is not on the entity.)
# Region: /test_tb/sysgen_dut/gateway_out_13_obuf
# ** Error: (vsim-3733) ./netgen/par/test_cw_timesim.vhd(14910): No default binding for component at 'gateway_out_14_obuf'.
# (Generic 'tpd_gts_o' is not on the entity.)
# Region: /test_tb/sysgen_dut/gateway_out_14_obuf
# ** Error: (vsim-3733) ./netgen/par/test_cw_timesim.vhd(1491: No default binding for component at 'gateway_out_15_obuf'.
# (Generic 'tpd_gts_o' is not on the entity.)

# Loading simprim.x_dsp48e(x_dsp48e_v)
# Loading simprim.x_srlc16e(x_srlc16e_v)
# Loading simprim.x_ckbuf(x_ckbuf_v)
# Loading simprim.x_roc(x_roc_v)
# Loading simprim.x_toc(x_toc_v)
# Loading instances from ./netgen/par/test_cw_timesim.sdf
# Loading timing data from ./netgen/par/test_cw_timesim.sdf
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./pn_postpar.do PAUSED at line 15


Note that my pn_postpar.do file is generated by Sys Gen automatically as follows, the line 15 is the vsim command.


-- If you see error messages concerning missing libraries for
-- XilinxCoreLib, unisims, or simprims, you may not have set
-- up your ModelSim environment correctly. See the Xilinx
-- Support Website for instructions telling how to compile
-- these libraries.

vlib work

vcom -93 -nowarn 1 -novopt "D:/Xilinx/10.1/DSP_Tools/common/bin/../../sysgen/hdl/conv_pkg.vhd"
vcom -93 -nowarn 1 -novopt "D:/Xilinx/10.1/DSP_Tools/common/bin/../../sysgen/hdl/xlclkprobe.vhd"
set env(PERL5LIB) {}
exec "D:/Xilinx/10.1/ISE/bin/nt/unwrapped/xilperl.exe" "D:/Xilinx/10.1/DSP_Tools/common/bin/../../sysgen/scripts/probeclk.pl" -f ./netgen/par/test_cw_timesim.vhd
vcom -nowarn 1 -novopt ./netgen/par/test_cw_timesim.vhd
vcom -93 -nowarn 1 -novopt test_tb.vhd
vsim -novopt -L work -t ps -sdftyp /sysgen_dut=./netgen/par/test_cw_timesim.sdf test_tb
view wave
add wave *
view structure
view signals
run 6875.000000 ns


Anybody have ideas?
 
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