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VHDL2008 generate syntax

 
 
Tricky
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      03-19-2010
Im trying to use the new if/elseif/else generate syntax. Modelsim is
throwing up an error for me, but quartus 9.1 likes it:

test_gen : if test generate
g <= '1';
else
g <= '0';
end generate test_gen;

Modelsim 6.5 gives me the error: "Near Else - syntax error"

Same problem with the case version - quartus doesnt mind but modelsim
complain's that there is no "is"

test_gen : case test generate
when true =>
g <= '1';
when false =>
g <= '0';
end generate test_gen;

Am I missing something in the syntax - or have a missed a modelsim
compile setting (Ive switched to 2008 in compile mode in modelsim).

Any ideas?
 
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HT-Lab
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Posts: n/a
 
      03-19-2010
Unfortunately this is not yet supported in Modelsim (not even the latest 6.5e
which was released last week

Email your Mentor rep and ask him to open an ER,

Regards,
Hans
www.ht-lab.com

"Tricky" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> Im trying to use the new if/elseif/else generate syntax. Modelsim is
> throwing up an error for me, but quartus 9.1 likes it:
>
> test_gen : if test generate
> g <= '1';
> else
> g <= '0';
> end generate test_gen;
>
> Modelsim 6.5 gives me the error: "Near Else - syntax error"
>
> Same problem with the case version - quartus doesnt mind but modelsim
> complain's that there is no "is"
>
> test_gen : case test generate
> when true =>
> g <= '1';
> when false =>
> g <= '0';
> end generate test_gen;
>
> Am I missing something in the syntax - or have a missed a modelsim
> compile setting (Ive switched to 2008 in compile mode in modelsim).
>
> Any ideas?



 
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