The fixed point packages can be used, by specifying zero fractional

(negative indexed) bits, to represent signed and unsigned integer

arithmetic. The fixed point packages assume a more integer-like tilt

toward numeric accuracy than numeric_std does, by expanding the sizes

of results to accurately handle the possible nnumeric range of those

results. So adding two n bit ufixed operands results in an n+1 bit

result. This means that intermediate results in expressions are

numerically accurate (not subject to truncation, except for division),

but due to the inability to override assignment operators in VHDL, the

results usually must be manually re-sized to store in a variable or

signal. Just like with integers, synthesis should be able to do a good

job of removing bits and logic associated with expanded intermediate

results if they do not contribute to those bits retained in storage.

So an up counter would look something like:

variable n : ufixed(nsize - 1 downto 0);

....

-- resize does the rollover

n := resize(n + 1, n);

My biggest disappointment with the fixed point package is that

subtraction of two ufixed operators does not expand the result to

sfixed (but it does expand the size of the results by one bit, which

will always be zero!) So while the ufixed + operator does not roll

over, the - operator for ufixed does, however by some perverse stroke

of luck, you still have to manually resize the result:

variable n : ufixed(nsize - 1 downto 0);

....

-- ufixed subtract does the rollover,

-- resize is still required

n := resize(n - 1, n);

Comparatively, with integers:

variable n : integer range 0 to 2**nsize - 1;

....

-- integer mod does the rollover

n := (n - 1) mod 2**nsize;

And with unsigned:

variable n : unsigned(nsize - 1 downto 0);

....

-- unsigned subtract does the rollover

n := n - 1;

Andy