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[Luca D.]

Hi all!
I've just started to study how the synthesis process works and can't find any information about what happens when values different from '1' and '0' are used for a std_logic signal.
For example, given the following code:

case x is
  when '1' => y <= '0';
  when '0' => y <= '1';
  when others => y <= 'X';

How would the circuit be synthesised?
And which will be the difference if in the last line y gets assigned 'Z' or '-'?

Thank you so much!
Bye