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When others case and Synthesis

 
 
Luca D. Luca D. is offline
Junior Member
Join Date: Mar 2010
Posts: 1
 
      03-05-2010
Hi all!
I've just started to study how the synthesis process works and can't find any information about what happens when values different from '1' and '0' are used for a std_logic signal.
For example, given the following code:
Code:
case x is
  when '1' => y <= '0';
  when '0' => y <= '1';
  when others => y <= 'X';
How would the circuit be synthesised?
And which will be the difference if in the last line y gets assigned 'Z' or '-'?

Thank you so much!
Bye
 
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