On Feb 18, 7:14*pm, "Brad Smallridge" <(EMail Removed)>
wrote:
> Hello VHDL group,
>
> I have a need to translate a natural generic
> into a 0 or 1 constant something like:
>
> entity . . .
> generic(sim : natural . . .
> port( ...
> constant sim01 : natural := 0 if sim=0, else :=1;
> . . .
> begin
> . . .
>
> but of course this syntax doesn't fly.
>
> Brad
Sometimes I find I like 'C' where you can implement a 2>1 selection
quite concisely
c = cond: a ? b; (at least I think that's the syntax).
So much so, that I create a select function 'sel' that works
similarly...and then override it to work with all the basic data types
function sel(Cond: BOOLEAN; A, B: integer) return integer;
function sel(Cond: BOOLEAN; A, B: real) return real;
function sel(Cond: BOOLEAN; A, B: time) return time;
etc.
function sel(Cond: std_ulogic; A, B: integer) return integer;
function sel(Cond: std_ulogic; A, B: real) return real;
function sel(Cond: std_ulogic; A, B: time) return time;
etc.
While it's a bit of pain (but only one time) to create these headers,
the function body itself is a straight copy and paste with virtually
no editing for each variant.
begin
if (Cond = '1') then
return(A);
else
return(B);
end if;
end function sel;
I package that all up in a package with other generally useful
functions that I routinely use so that for the example you want, I can
simply say
constant sim01 : natural := sel(sim, 0,1);
Kevin Jennings
