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Component selection in ISE

 
 
sridar sridar is offline
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Join Date: Jun 2007
Posts: 52
 
      02-09-2010
Hey all,

I want to bind any of the two components (written using VHDL) to the top module and I don't want the other component to be synthesized while synthesizing the top module.

But xilinx ISE synthesize all the components in the top module.

The components are complex than the simple gates considered in example below.

------ code example

entity top
.
.
.

architecture top
..
..
begin

-- gatesel is declared in package

If (gatesel=1) generate
a1: andg port map(....);
end generate;

If (gatesel=2) generate
a1: org port map(....);
end generate;

If (gatesel=3) generate
a1: xorg port map(....);
end generate;
 
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