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Identity-conversion of the clock signal

valentin tihhomirov
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I have also suddenly realized that in my VHDL netlist writer
(unfortunately I do not use EDIF, which does not demand line type
specification) I extensively use intermediate clock assignments: between
parent port and instances. I have just realized how dangerous this might
be. But surprisingly, I have never faced any problems because of this:
neither in sim nor in synthesis.
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On Jan 25, 1:49*pm, valentin tihhomirov <(E-Mail Removed)> wrote:
> >> IMO, assignments exist in all languages for one important thing: you
> >> compute once and save/share the result.

> > Variable assignment meets that need in VHDL.

> Variables are used to generate logic in the process. They represent
> different signals at different times. And, they are hard-to-debug in
> simulator.

While some simulators cannot show variables in waveforms, I prefer to
use the source level debugger with break points, assertion statements,
etc. to debug anyway. Besides, the SLD shows you all the stuff that is
happening in zero time, which is largely unavailable in waveforms.
Representing both combinatorial and registered logic with one variable
is much easier to comprehend in a source level debugger than in a
waveform. A given reference to a variable represents one thing (the
output of either gate or a register), and that is what you see at a
breakpoint or a triggered sequential assertion statement in the SLD.

Think about clock-cycle-based behavior first, then worry about
implementation (gates and registers), and variables will open a whole
new way of looking at HDL. Then, after your synthesizer is finished
with register replication, retiming, duplicate removal and other
optimizatoins, your behavioral description will still make sense,
while an implementation based description may not.

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