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Conditional compiling, exists ?

 
 
LC
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      01-19-2010
Hi.

Sorry for the naive question.

Is there a way to implement conditional compiling
in VHDL (as in C for example, #ifdef... #endif).

I would like to have a source with two variants
that I may decide to compile one way or another
but there are several small differences spread
across the code so...

(two separate files is difficult to maintain in sync
while design progresses)
(commenting and uncommenting parts is prone to mistakes
and messy)

Is there any hope to make my life easier ?


Luis. C.

 
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joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
 
      01-19-2010
Inside a process you can simply use if statements, checking whether a constant boolean is true or similar;
Code:
  if ( DO_MANUAL_CHECK ) then 
    -- any valid code inside a process
  else
    -- alternative code inside the process
  end if;
The else case is optional obviously;

Outside of a process, you can do something similar, using the if generate construct:
Code:
checked: if ( DO_MANUAL_CHECK ) generate
    -- any valid code inside the body of an architecture
  end generate checked;

alt_checked: if ( not DO_MANUAL_CHECK ) generate
    -- alternative code inside the body of the architecture
  end generate alt_checked;
An if-generate is required to have a label ("checked" in this case)
There is not "else" part for the if-generate construct, so you have to add another if-generate, testing
for the not case.

Any synthesizer will pick up that the check is always true (or always false), so it will do what you expect.
 

Last edited by joris; 01-19-2010 at 02:24 PM..
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Tricky
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      01-19-2010
On 19 Jan, 14:03, LC <(E-Mail Removed)> wrote:
> Hi.
>
> Sorry for the naive question.
>
> Is there a way to implement conditional compiling
> in VHDL (as in C for example, #ifdef... #endif).
>
> I would like to have a source with two variants
> that I may decide to compile one way or another
> but there are several small differences spread
> across the code so...
>
> (two separate files is difficult to maintain in sync
> while design progresses)
> (commenting and uncommenting parts is prone to mistakes
> and messy)
>
> Is there any hope to make my life easier ?
>
> Luis. C.


I think there may be a couple of options:

1. Have 2 different architectures for the same entity and use
configurations to change which one to compile
2. Use generics to control what gets compiled based on the values:

for example:

reg_gen : if add_register generate

process(clk)
begin
if rising_edge(clk) then
out <= in;
end if;
end process;
end reg_gen

no_reg_gen : if not add_register generate

out <= in;
end no_reg_gen;


Given what you already said (2 variants on the same thing) you
probably want configurations (someone else will have to explain this
mystical VHDL concept).
 
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Rich Webb
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      01-19-2010
On Tue, 19 Jan 2010 14:03:57 +0000, LC <(E-Mail Removed)> wrote:

>Hi.
>
>Sorry for the naive question.
>
>Is there a way to implement conditional compiling
>in VHDL (as in C for example, #ifdef... #endif).
>
>I would like to have a source with two variants
>that I may decide to compile one way or another
>but there are several small differences spread
>across the code so...
>
>(two separate files is difficult to maintain in sync
>while design progresses)
>(commenting and uncommenting parts is prone to mistakes
>and messy)
>
>Is there any hope to make my life easier ?


You might want to look at "m4" which is a macro preprocessor intended as
a front end to the "normal" compilation process. It's a pretty standard
Unix utility (or did it pre-date Unix?) that's now on most (all?) *ix
distributions. There are binary versions for Windows (Cygwin and native
code) and Mac.

For more info, hop over to the Wikipedia entry and go from there.

--
Rich Webb Norfolk, VA
 
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Petter Gustad
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      01-19-2010
LC <(E-Mail Removed)> writes:

> Is there a way to implement conditional compiling
> in VHDL (as in C for example, #ifdef... #endif).


See generate.

Petter
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Mike Treseler
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      01-19-2010
LC wrote:

> Is there a way to implement conditional compiling
> in VHDL (as in C for example, #ifdef... #endif).


There is no preprocessor.
I use packaged constants with regular
vhdl conditional statements or generics.

-- Mike Treseler
 
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LC
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      01-20-2010
Many thanks for the tips.

LC.
 
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LC
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      01-20-2010
Alan Fitch wrote:
> LC wrote:
>> Many thanks for the tips.
>>
>> LC.

>
> Hi LC,
> we also have a little technote about this very issue:
>
> http://www.doulos.com/knowhow/fpga/t....php#Technote2
>
> regards
> Alan
>
> P.S. We ask you to register for it - but as I remember there's a tickbox
> somewhere for you to opt out of being contacted again if you don't want
> to be, Alan
>
>


Hi Alan,

I could not imagine a better technote on the subject
You guys rock !

Many Thanks.

Luis C.


 
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