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vhdl / verilog comparing

 
 
Mike Treseler
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      01-12-2010
Petter Gustad wrote:

> Why is single process with no signals more advanced when it comes to
> synthesis?


That is certainly a matter of opinion.
Structural vs procedural.
I prefer using variables, functions, and procedures
in a single box instead of modules upon modules.

-- Mike Treseler
 
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Andy
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      01-12-2010
On Jan 11, 9:45*pm, Mike Treseler <(E-Mail Removed)> wrote:
> Petter Gustad wrote:
> > Why is single process with no signals more advanced when it comes to
> > synthesis?

>
> That is certainly a matter of opinion.
> Structural vs procedural.
> I prefer using variables, functions, and procedures
> in a single box instead of modules upon modules.
>
> * *-- Mike Treseler


I also prefer the immediate update semantics of variables as opposed
to the postponed updates of signals in processes. "I stored this in
the sig up here, but it still has the old value down here later...".

Using variables often makes it easier to insert/remove clock cycles in
your behavioral description. Two references to the same variable can
be registered or combinatorial values independently. The synthesis
tool will do what it takes to create HW that mimics the clock cycle
behavior of your code, which now reads like SW code, without the
postponed values issues. It also makes more sense when using the
source level debugger.

These may or may not be "advantages" to other users.

Andy
 
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Petter Gustad
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      01-17-2010
Mike Treseler <(E-Mail Removed)> writes:

> Petter Gustad wrote:
>
>> Why is single process with no signals more advanced when it comes to
>> synthesis?

>
> That is certainly a matter of opinion.


I see, so it's more a matter of taste.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
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Petter Gustad
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      01-17-2010
Andy <(E-Mail Removed)> writes:

> I also prefer the immediate update semantics of variables as opposed
> to the postponed updates of signals in processes. "I stored this in
> the sig up here, but it still has the old value down here later...".


Yuck. Synthesizable Ada comes to my mind. I guess I'm a little old
fashioned in this regard.


Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
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Petter Gustad
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      01-17-2010
David Bishop <(E-Mail Removed)> writes:

> Verilog was written by a bunch of hardware guys who knew nothing about
> software. We beat on it 'till you could do software with it.


Still I prefer SystemVerilog over VHDL for writing testbenches
using classes, constrained random generation, covergroups, queues,
assertions, and other software constructs.

> VHDL was written by a bunch of software guys who knew nothing about
> hardware. We beat on it 'till you could do hardware with it.


Still I prefer VHDL over Verilog for writing DUT's.


Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
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Mike Treseler
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      01-17-2010
Petter Gustad wrote:

>>> Why is single process with no signals more advanced when it comes to
>>> synthesis?

>> That is certainly a matter of opinion.

>
> I see, so it's more a matter of taste.


Yes. Bud Lite vs IPA
 
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