On Mon, 4 Jan 2010 03:03:25 -0800 (PST), hssig wrote:

>signal numa : unsigned(2 downto 0);

>

>constant cA : unsigned(2 downto 0) := "000";

>constant cB : unsigned(2 downto 0) := "001";

>constant cC : unsigned(2 downto 0) := "100";

>

>process(rstn, clk)

>begin

> if rstn='0' then

> numa <= "000";

>

> elsif rising_edge(clk) then

> ...

>

> case to_integer(numa) is

> when to_integer(cA) => ...

> when to_integer(cB) to to_integer(cC) => ...

> when others => ...

> end case;

>

> end if;

>

>end process;

>"ERROR: case choice must be a locally static expression (VHDL-143"

>

>How can I make use of the discrete range choice without violating the

>static expression rule ?
"Locally static" in VHDL is a very aggressive restriction and

there's not much you can do about it. Function call in the

case choice is a no-no, sorry.

I suggest you re-cast your code so that the original constants

are integers:

--- Useful bits and pieces

subtype u3 is unsigned(2 downto 0);

subtype i3 is integer range 0 to (2**u3'length - 1);

function to_u3(n: i3) return u3 is begin

return to_unsigned(n, u3'length);

end;

--- Your constants as proper integers

constant nA : i3 := 0;

constant nB : i3 := 1;

constant nC : i3 := 4;

--- Your unsigned signals and constants,

--- derived from the original integers

signal numa: u3;

constant cA: u3 := to_u3(nA);

constant cB: u3 := to_u3(nB);

constant cC: u3 := to_u3(nC);

--- Now the case statement should be OK,

--- as well as being easier to read:

case to_integer(numa) is

when nA => ...

when nB to nC => ...

when others => ...

end case;

Hope this helps

--

Jonathan Bromley