Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Co simulation of SystemC files with VHDL testbench

Reply
Thread Tools

Co simulation of SystemC files with VHDL testbench

 
 
doromdor doromdor is offline
Junior Member
Join Date: Nov 2009
Posts: 2
 
      12-07-2009
Sorry if this is not the correct place to post my question,

I am intrested in co-simulation of VHDL and systemC

I want to use VHDL testbench in order to test systemC files

The programs I am using for this are Questasim and Modelsim (of mentor graphics)

Anyone has a good tutorial about this or can explain me how it is done ?



Thanks in advance ,

Dor
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
question regarding modelsim - systemC testbench doromdor VHDL 0 11-17-2009 09:19 PM
Modelsim6.2f with gcc 3.4.4-----for SystemC simulation Neha VHDL 4 06-08-2008 09:36 AM
Problem during mixed VHDL SystemC simulation with Modelsim 6.2a Steven Derrien VHDL 2 07-13-2006 09:50 AM
SystemC + VHDL cosim, hierarchy probing, etc... jjohnson@cs.ucf.edu VHDL 2 12-20-2004 05:05 PM
Reset simulation with systemC nicolai@free.fr VHDL 1 06-25-2004 09:43 AM



Advertisments