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Co simulation of SystemC files with VHDL testbench

doromdor doromdor is offline
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Join Date: Nov 2009
Posts: 2
Sorry if this is not the correct place to post my question,

I am intrested in co-simulation of VHDL and systemC

I want to use VHDL testbench in order to test systemC files

The programs I am using for this are Questasim and Modelsim (of mentor graphics)

Anyone has a good tutorial about this or can explain me how it is done ?

Thanks in advance ,

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