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simulation limit

 
 
JSreeniv
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      12-07-2009
Hi all,

I have a query regarding to the post route simulation(timing
simulation) using Modelsim, presently i am using 6.4 PE.
In first i am done Functional simulation using VHDL test bench
implementation, and when "End of Test" assertion reached and
simulator will stop from assertion Failure condition; now i got let
say end time of simulation is 10 us.

Now loaded necessary files to run timing simulation; now i want to
know how to decide to give end of simulation time to run; where as
this timing simulation will take account all the gates, paths
etc..delays. so appending on the time from where i got functional
simulation is fine or need to have some analysis? To give end run time
simulation.

Please give some exposure on this issue..
 
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joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
 
      12-07-2009
you can add an "assertion" like this to the very end of the test bench, just to get a final message:
Code:
assert false report "end of testbench" severity note;
 
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Mike Treseler
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      12-07-2009
JSreeniv wrote:

> Now loaded necessary files to run timing simulation; now i want to
> know how to decide to give end of simulation time to run; where as
> this timing simulation will take account all the gates, paths
> etc..delays. so appending on the time from where i got functional
> simulation is fine or need to have some analysis? To give end run time
> simulation.


If I use the same testbench, the sim time is the same
but the coffee drinking time may be ten times longer.

By the way, a gate sim is a test of your
tools, rules and testbench, not your design.

-- Mike Treseler
 
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Thomas Stanka
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      12-08-2009
On 7 Dez., 18:40, Mike Treseler <(E-Mail Removed)> wrote:
> JSreeniv wrote:
> > Now loaded necessary files to run timing simulation; now i want to
> > know how to decide to give end of simulation time to run; where as
> > this timing simulation will take account all the gates, paths
> > etc..delays. so appending on the time from where i got functional
> > simulation is fine or need to have some analysis? To give end run time
> > simulation.

>
> If I use the same testbench, the sim time is the same
> but the coffee drinking time may be ten times longer.
>
> By the way, a gate sim is a test of your
> tools, rules and testbench, not your design.


You should add your skill in using this tools .
Too often happens that simualtion shows an error made in timing
analysis not by tool but by developer.

regards Thomas
 
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