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Hi all,

I am implementing a serial protocol and I am saving the data and
status bits in 4, 8 bit registers. I have declared an array of 4,
std_logic_vectors 8 bits long using a type.

Now I need an alias for a single bit in the array, example ACK = bit 0
of register 2.

What is the correct syntax to declare it?

I have another question. I have testing out Xilinx ISE and Synplify.
Does each software has its own quirks when writing synthesizable VHDL?
I think the best option is to choose a product and stick with it?

Thanks very much,

Regards,

Joseph

On 3 Dec, 06:59, Joseph <joz...@gmail.com> wrote:
> Hi all,
>
> I am implementing a serial protocol and I am saving the data and
> status bits in 4, 8 bit registers. I have declared an array of 4,
> std_logic_vectors 8 bits long using a type.
>
> Now I need an alias for a single bit in the array, example ACK = bit 0
> of register 2.
>
> What is the correct syntax to declare it?

To create an alias, here is the syntax:

alias ACK : std_logic is my_registers(2)(0);

But according to my Doulos book aliases are not supported by all tools
(I dont really use them, so cant comment on quartus). Why dont yo just
maintain ACK as a single bit register and attach it to the output,
like:

ACK_reg : process(clk)
begin
if rising_edge(clk) then
ACK <= some function;
end if;
end process;

my_regs(2)(0) <= ACK;

This way ACK is always its own register, just tied into a bus.

>
> I have another question. I have testing out Xilinx ISE and Synplify.
> Does each software has its own quirks when writing synthesizable VHDL?
> I think the best option is to choose a product and stick with it?
>

Yes, that is what most people do, normally because the licencing for
the tools is so expensive. But aslong as you keep to the basic coding
templates you shouldnt hit a problem with any tools.

> On 3 Dec, 06:59, Joseph <joz...@gmail.com> wrote:
>> Hi all,
>>
>> I am implementing a serial protocol and I am saving the data and
>> status bits in 4, 8 bit registers. I have declared an array of 4,
>> std_logic_vectors 8 bits long using a type.
>>
>> Now I need an alias for a single bit in the array, example ACK = bit 0
>> of register 2.

I prefer naming bit fields from the bottom up.
If I first declare ACK and all the other bits
as std_ulogic signals or variables,
I am free to update or structure
them by name, however I like.

Tricky wrote:

> To create an alias, here is the syntax:
> alias ACK : std_logic is my_registers(2)(0);
>
> But according to my Doulos book aliases are not supported by all tools
> (I don't really use them, so cant comment on quartus).

Last I tried, modelsim supports aliases, but does not make them
visible. I could see the underlying object, but not the aliased fields.
This made aliases very uninteresting to me.
So now if I want to see a label, I declare the field as a vhdl object.
But this may have changed. Try it and see.

> Why don't you just
> maintain ACK as a single bit register and attach it to the output...

I agree.
Since I have to declare something in either case,
I see no upside to aliases for sim or synthesis.


-- Mike Treseler