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Re: Syntax question about aliases

 
 
Daku
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Posts: n/a
 
      11-26-2009
You could try concatenating them, much like in Verilog.

On Nov 25, 11:27 pm, Rob Gaddi <(E-Mail Removed)> wrote:
> Is there any way to alias a group of discrete signals into an array? I
> know I could do a bunch of individual assignments, but I'm looking for
> something a bit cleaner. For instance:
>
> --
>
> entity Critter is
> Port (
> this : in std_logic;
> that : in std_logic;
> the_other : in std_logic;
>
> this_q : out std_logic;
> that_q : out std_logic;
> the_other_q : out std_logic;
>
> clk : in std_logic
> );
> end entity Critter;
>
> architecture Behavioural of Critter is
>
> alias inputs : std_logic_vector(2 downto 0)
> is this & that & the_other;
>
> alias outputs : std_logic_vector(2 downto 0)
> is this_q & that_q & the_other_q;
>
> begin
>
> outputs <= inputs when rising_edge(clk);
>
> end architecture Behavioural;
>
> --
>
> Thanks,
> Rob
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order


 
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