Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > General Computer Discussion > Software > Asynchronous Logic Gates and Analog Logic Gates

Reply
Thread Tools

Asynchronous Logic Gates and Analog Logic Gates

 
 
Jyoti Ballabh Jyoti Ballabh is offline
Member
Join Date: Sep 2009
Posts: 44
 
      11-23-2009
A food for thought for the real programmers.

What can you infer from the following codes?

program mcint
write{*,1}
format{' enter number of sampling points to be used' }
read (*,*)n
write {*,2}
format (' enter random seed ')
read {*,*} idum
sum=0.0
sum2=0.0
do 10 i = 1,n
x=10.0*rand {idum)
y=10.0*rand {idum)
z=10.0*rand (idum}
fx=x**2*exp(-x}
fy=y**2*exp(-y}
fz=z**2*exp(-z}
fun=fx*fy*fz
sum=sum+fun
sum2=sum2+fun*fun
value=1000.0*sum/n
unc=1000.0*sqrt({{sum2/n}-{sum/n}**2)/n}
write (*,11) value, unc
format {' Integral value: ', f10.5,' +/-', f10.5}
stop
end
function rand(ix}
integer a,p,ix,b15,b16,xhi,xalo,leftlo,fhi,k
data a/16807/,b15/32768/,b16/65536/,p/2147483647
xhi= ix/b16
xalo= (ix-xhi*b16}*a
leftlo= xalo/b16
fhi= xhi*a+leftlo
k=fhi/b15]
ix= ({{xalo-leftlo*b16)-p)+ (fhi-k*b15}*b16}+k
if(ix.lt.0}ix=ix+p
rand= float(ix)*4.656612875e-10
return
end
 
Reply With Quote
 
 
 
 
Jyoti Ballabh Jyoti Ballabh is offline
Member
Join Date: Sep 2009
Posts: 44
 
      11-26-2009
Asynchronous Logic Automation and Analog Logic Automation. Yea, you are right. This does deal with the cellular microcode configuration in the super computer architecture. I hate it when my threads are deleted. Like I said, there is nothing I can do about it.
 
Reply With Quote
 
 
 
 
Jyoti Ballabh Jyoti Ballabh is offline
Member
Join Date: Sep 2009
Posts: 44
 
      11-26-2009
50 by next half an hour!
 
Reply With Quote
 
Jyoti Ballabh Jyoti Ballabh is offline
Member
Join Date: Sep 2009
Posts: 44
 
      11-26-2009
I should start with a brain teaser section of my own. there is only so much product launch info that you could post on a site like this and only so many product related issues.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Python Logic Map/Logic Flow Chart. (Example Provided) spike Python 8 02-09-2010 12:31 PM
Representing the buffer with logic gates,flipflops KSR VHDL 13 11-06-2009 06:02 PM
uninferred due to asynchronous read logic Shannon VHDL 25 05-14-2008 04:22 PM
Introduction to Logic Gates Silverstrand Front Page News 0 10-24-2005 01:44 PM
Want to simulate logic gates usao VHDL 1 04-14-2004 07:36 AM



Advertisments