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Could some VHDL guru please shed some light as to what my problem
might be ?
In my architecture description I have :
ARCHITECTURE dataflow_view OF ram IS
CONSTANT MAX : integer := 32;
SIGNAL index : std_logic_vector (0 to 31);
SIGNAL position : integer RANGE 0 TO MAX - 1;

BEGIN
index <= (OTHERS => 0);
position <= 0;

RAM_0 : PROCESS( WEB )
VARIABLE head : INTEGER RANGE 0 TO MAX - 1;

BEGIN
head := 0;

IF (WEB='1' AND WEB'EVENT )
THEN IF (REB='0') THEN
IF (index(0) = '0') THEN
index(0) <= '1';
END IF;
END IF;
END IF;

END PROCESS RAM_0;

I am getting a compile time error message about illegal assignment.

My goal is to iterate over the elements of the std_logic_vector index,
and depending on whether it has value '0' set it to '1' and then
assign values to another signal. Could someone please point out what
the error might be ?
Any hints, suggestions would be of immense help. Thanks in advance for
your help.

[jeppe]

In my architecture description I have :
ARCHITECTURE dataflow_view OF ram IS
CONSTANT MAX : integer := 32;
SIGNAL index : std_logic_vector (0 to 31) := (others =>'0');
SIGNAL position : integer RANGE 0 TO MAX - 1;

BEGIN
-- index <= (OTHERS => 0); -- This assignment not allowed together with the process assignment.
position <= 0;

RAM_0 : PROCESS( WEB )
VARIABLE head : INTEGER RANGE 0 TO MAX - 1;

BEGIN
head := 0;

IF (WEB='1' AND WEB'EVENT )
THEN IF (REB='0') THEN
IF (index(0) = '0') THEN
index(0) <= '1';
END IF;
END IF;
END IF;

END PROCESS RAM_0;

Hopefully will this help you