what does this error means in vhdl(xilinx)

vhdl-fpga

Junior Member

Join Date: Nov 2009

Posts: 1

11-19-2009

Running ISim simulation engine ...
ERROR:Simulator:29 - at 0 ns : in arctest(testbench_arch), file
C:/Xilinx92i/arch/arctest.vhw: Default port map for entity arc to component
arc connects std_ulogic type local port C2 of the component to BIT type port
of the entity.
ERROR:Simulator:29 - at 0 ns :
This is a Lite version of ISE Simulator.

plz do reply asap

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